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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 2/2] arm64: dts: qcom: sm8450: Mark UFS controller as cache
coherent
Date: Tue, 7 Mar 2023 21:02:01 +0530
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[1/2] arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent
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Commit Message
Manivannan Sadhasivam
March 7, 2023, 3:32 p.m. UTC
The UFS controller on SM8450 supports cache coherency, hence add the
"dma-coherent" property to mark it as such.
Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 +
1 file changed, 1 insertion(+)
Comments
On 07/03/2023 16:32, Manivannan Sadhasivam wrote: > The UFS controller on SM8450 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Fixes: 07fa917a335e ("arm64: dts: qcom: sm8450: add ufs nodes") > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 1a744a33bcf4..3ef47b4e9af7 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -4003,6 +4003,7 @@ ufs_mem_hc: ufshc@1d84000 { > power-domains = <&gcc UFS_PHY_GDSC>; > > iommus = <&apps_smmu 0xe0 0x0>; > + dma-coherent; > > interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, > <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..3ef47b4e9af7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4003,6 +4003,7 @@ ufs_mem_hc: ufshc@1d84000 { power-domains = <&gcc UFS_PHY_GDSC>; iommus = <&apps_smmu 0xe0 0x0>; + dma-coherent; interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;