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From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: andersson@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Subject: [PATCH 1/2] arm64: dts: qcom: sm8350: Mark UFS controller as cache
coherent
Date: Tue, 7 Mar 2023 21:02:00 +0530
Message-Id: <20230307153201.180626-1-manivannan.sadhasivam@linaro.org>
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[1/2] arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent
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Commit Message
Manivannan Sadhasivam
March 7, 2023, 3:32 p.m. UTC
The UFS controller on SM8350 supports cache coherency, hence add the
"dma-coherent" property to mark it as such.
Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 +
1 file changed, 1 insertion(+)
Comments
On 07/03/2023 16:32, Manivannan Sadhasivam wrote: > The UFS controller on SM8350 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Fixes: 59c7cf814783 ("arm64: dts: qcom: sm8350: Add UFS nodes") > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 1c97e28da6ad..1a5a612d4234 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -1664,6 +1664,7 @@ ufs_mem_hc: ufshc@1d84000 { > power-domains = <&gcc UFS_PHY_GDSC>; > > iommus = <&apps_smmu 0xe0 0x0>; > + dma-coherent; > > clock-names = > "core_clk", Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Tue, 7 Mar 2023 21:02:00 +0530, Manivannan Sadhasivam wrote: > The UFS controller on SM8350 supports cache coherency, hence add the > "dma-coherent" property to mark it as such. > > Applied, thanks! [1/2] arm64: dts: qcom: sm8350: Mark UFS controller as cache coherent commit: e607b3c1fa0e1579951acd00f9559a77f97d0927 [2/2] arm64: dts: qcom: sm8450: Mark UFS controller as cache coherent commit: 8ba961d4339c5db0e69ff6627606fe1f34c838e5 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 1c97e28da6ad..1a5a612d4234 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1664,6 +1664,7 @@ ufs_mem_hc: ufshc@1d84000 { power-domains = <&gcc UFS_PHY_GDSC>; iommus = <&apps_smmu 0xe0 0x0>; + dma-coherent; clock-names = "core_clk",