diff mbox series

[v1,1/2] scripts: generate_rust_target: enable building on RISC-V

Message ID 20230307102441.94417-2-conor.dooley@microchip.com
State New
Headers
Series RISC-V: enable rust |

Commit Message

Conor Dooley March 7, 2023, 10:24 a.m. UTC 
  From: Miguel Ojeda <ojeda@kernel.org>

Add the required bits from rust-for-linux to enable generating a RISC-V
target for rust. The script, written by Miguel, was originally a
config file contributed by Gary.

Co-developed-by: Gary Guo <gary@garyguo.net>
Signed-off-by: Gary Guo <gary@garyguo.net>
Signed-off-by: Miguel Ojeda <ojeda@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Despite removing 32-bit support, I kept the structure of the if
statement, despite early return being stylistically preferred, for
alignment with the Rust-for-Linux tree. I'm happy to respin to sort that
out of desired.
---
 scripts/generate_rust_target.rs | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Miguel Ojeda March 7, 2023, 11:21 a.m. UTC | #1 
On Tue, Mar 7, 2023 at 11:25 AM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> Despite removing 32-bit support, I kept the structure of the if
> statement, despite early return being stylistically preferred, for
> alignment with the Rust-for-Linux tree. I'm happy to respin to sort that
> out of desired.

This is a case of 2 "equal" sides to the branch (though at the moment
an error), so it sounds good, and it will mean a smaller diff later.

> +            panic!("32-bit RISC-V is an unsupported architecture")

Nit: if there is a v2, please add a semicolon to be consistent with
the others in the file (not sure which style we will go for, it looks
like `rustfmt` accepts both ways).

Cheers,
Miguel
diff mbox series

Patch

diff --git a/scripts/generate_rust_target.rs b/scripts/generate_rust_target.rs
index 3c6cbe2b278d3..85d690f764389 100644
--- a/scripts/generate_rust_target.rs
+++ b/scripts/generate_rust_target.rs
@@ -161,6 +161,22 @@  fn main() {
         ts.push("features", features);
         ts.push("llvm-target", "x86_64-linux-gnu");
         ts.push("target-pointer-width", "64");
+    } else if cfg.has("RISCV") {
+        if cfg.has("64BIT") {
+            ts.push("arch", "riscv64");
+            ts.push("data-layout", "e-m:e-p:64:64-i64:64-i128:128-n64-S128");
+            ts.push("llvm-target", "riscv64-linux-gnu");
+            ts.push("target-pointer-width", "64");
+        } else {
+            panic!("32-bit RISC-V is an unsupported architecture")
+        }
+        ts.push("code-model", "medium");
+        ts.push("disable-redzone", true);
+        let mut features = "+m,+a".to_string();
+        if cfg.has("RISCV_ISA_C") {
+            features += ",+c";
+        }
+        ts.push("features", features);
     } else {
         panic!("Unsupported architecture");
     }