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[05/19] PCI: qcom: Use lower case for hex

Message ID	20230306153222.157667-6-manivannan.sadhasivam@linaro.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Subject: [PATCH 05/19] PCI: qcom: Use lower case for hex Date: Mon, 6 Mar 2023 21:02:08 +0530 Message-Id: <20230306153222.157667-6-manivannan.sadhasivam@linaro.org> In-Reply-To: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> References: <20230306153222.157667-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Qcom PCIe cleanups and improvements \| [00/19] Qcom PCIe cleanups and improvements [01/19] PCI: qcom: Remove PCIE20_ prefix from register definitions [02/19] PCI: qcom: Sort and group registers and bitfield definitions [03/19] PCI: qcom: Use bitfield definitions for register fields [04/19] PCI: qcom: Add missing macros for register fields [05/19] PCI: qcom: Use lower case for hex [06/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 [07/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 [08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 [09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 [10/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 [11/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 [12/19] PCI: qcom: Use macros for defining total no. of clocks & supplies [13/19] dt-bindings: PCI: qcom-ep: Rename "mmio" region to "mhi" [14/19] PCI: qcom-ep: Rename "mmio" region to "mhi" [15/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs [16/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes [17/19] arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes [18/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes [19/19] PCI: qcom: Expose link transition counts via debugfs

Commit Message

Manivannan Sadhasivam March 6, 2023, 3:32 p.m. UTC

  To maintain uniformity, let's use lower case for representing hexadecimal
numbers.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 926a531fda3a..4179ac973147 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -39,17 +39,17 @@ 
 #define PARF_PCS_DEEMPH				0x34
 #define PARF_PCS_SWING				0x38
 #define PARF_PHY_CTRL				0x40
-#define PARF_PHY_REFCLK				0x4C
+#define PARF_PHY_REFCLK				0x4c
 #define PARF_CONFIG_BITS			0x50
 #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16C /* Register offset specific to IP ver 2.3.3 */
+#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
 #define PARF_MHI_CLOCK_RESET_CTRL		0x174
 #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
-#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1A8
-#define PARF_Q2A_FLUSH				0x1AC
-#define PARF_LTSSM				0x1B0
+#define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
+#define PARF_Q2A_FLUSH				0x1ac
+#define PARF_LTSSM				0x1b0
 #define PARF_SID_OFFSET				0x234
-#define PARF_BDF_TRANSLATE_CFG			0x24C
+#define PARF_BDF_TRANSLATE_CFG			0x24c
 #define PARF_SLV_ADDR_SPACE_SIZE		0x358
 #define PARF_DEVICE_TYPE			0x1000
 #define PARF_BDF_TO_SID_TABLE_N			0x2000
@@ -60,7 +60,7 @@ 
 /* DBI registers */
 #define AXI_MSTR_RESP_COMP_CTRL0		0x818
 #define AXI_MSTR_RESP_COMP_CTRL1		0x81c
-#define MISC_CONTROL_1_REG			0x8BC
+#define MISC_CONTROL_1_REG			0x8bc
 
 /* PARF_SYS_CTRL register fields */
 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN	BIT(29)