[v3,7/7] arm64: dts: qcom: sm8550: Use the correct BWMON fallback compatible

Message ID 20230304-topic-ddr_bwmon-v3-7-77a050c2fbda@linaro.org
State New
Headers
Series Fix BWMONv4 for <SDM845 |

Commit Message

Konrad Dybcio March 15, 2023, 2:11 p.m. UTC
  Use the correct fallback compatible for the BWMONv4 with merged global and
monitor register spaces.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Neil Armstrong March 16, 2023, 9:12 a.m. UTC | #1
On 15/03/2023 15:11, Konrad Dybcio wrote:
> Use the correct fallback compatible for the BWMONv4 with merged global and
> monitor register spaces.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 25f51245fe9b..b5488c6822bd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -3391,7 +3391,7 @@ opp-8 {
>   		};
>   
>   		pmu@240b6400 {
> -			compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon";
> +			compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
>   			reg = <0 0x240b6400 0 0x600>;
>   			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
>   			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> 

I can't test right now, but:

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
  

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 25f51245fe9b..b5488c6822bd 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3391,7 +3391,7 @@  opp-8 {
 		};
 
 		pmu@240b6400 {
-			compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon";
+			compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon";
 			reg = <0 0x240b6400 0 0x600>;
 			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
 			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;