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[V3,05/20] ACPI: OSL: Make should_use_kmap() 0 for RISC-V

Message ID	20230303133647.845095-6-sunilvl@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Sunil V L <sunilvl@ventanamicro.com> To: linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "Rafael J . Wysocki" <rafael@kernel.org>, Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, Jonathan Corbet <corbet@lwn.net>, Anup Patel <apatel@ventanamicro.com>, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@rivosinc.com>, 'Conor Dooley ' <conor.dooley@microchip.com>, Sunil V L <sunilvl@ventanamicro.com>, "Rafael J . Wysocki" <rafael.j.wysocki@intel.com> Subject: [PATCH V3 05/20] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Date: Fri, 3 Mar 2023 19:06:32 +0530 Message-Id: <20230303133647.845095-6-sunilvl@ventanamicro.com> In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add basic ACPI support for RISC-V \| [V3,00/20] Add basic ACPI support for RISC-V [V3,01/20] riscv: move sbi_init() earlier before jump_label_init() [V3,02/20] ACPICA: MADT: Add RISC-V INTC interrupt controller [V3,03/20] ACPICA: Add structure definitions for RISC-V RHCT [V3,04/20] ACPI: tables: Print RINTC information when MADT is parsed [V3,05/20] ACPI: OSL: Make should_use_kmap() 0 for RISC-V [V3,06/20] RISC-V: Add support to build the ACPI core [V3,07/20] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid [V3,08/20] drivers/acpi: RISC-V: Add RHCT related code [V3,09/20] RISC-V: smpboot: Create wrapper smp_setup() [V3,10/20] RISC-V: smpboot: Add ACPI support in smp_setup() [V3,11/20] RISC-V: ACPI: Cache and retrieve the RINTC structure [V3,12/20] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() [V3,13/20] RISC-V: cpu: Enable cpuinfo for ACPI systems [V3,14/20] irqchip/riscv-intc: Add ACPI support [V3,15/20] clocksource/timer-riscv: Refactor riscv_timer_init_dt() [V3,16/20] clocksource/timer-riscv: Add ACPI support [V3,17/20] RISC-V: time.c: Add ACPI support for time_init() [V3,18/20] RISC-V: Add ACPI initialization in setup_arch() [V3,19/20] RISC-V: Enable ACPI in defconfig [V3,20/20] MAINTAINERS: Add entry for drivers/acpi/riscv

Commit Message

Sunil V L March 3, 2023, 1:36 p.m. UTC

  Without this, if the tables are larger than 4K,
acpi_map() will fail.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 drivers/acpi/osl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index 3269a888fb7a..f725813d0cce 100644
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
@@ -276,7 +276,7 @@  acpi_map_lookup_virt(void __iomem *virt, acpi_size size)
 	return NULL;
 }
 
-#if defined(CONFIG_IA64) || defined(CONFIG_ARM64)
+#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
 /* ioremap will take care of cache attributes */
 #define should_use_kmap(pfn)   0
 #else