[12/15] arm64: dts: qcom: sm6375: Introduce MPM support
Commit Message
Add a node for MPM and wire it up on consumers that use it. This also
fixes a very bad and sad assumption I made when initially porting this
SoC that the downstream MPM-TLMM mappings were 1-1. That apparently
changed some time ago, so with this patch the MPM consumers will actually
be hooked up to the correct interrupt lines.
Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6375.dtsi | 32 ++++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
Comments
On 3.03.2023 22:58, Konrad Dybcio wrote:
> Add a node for MPM and wire it up on consumers that use it. This also
> fixes a very bad and sad assumption I made when initially porting this
> SoC that the downstream MPM-TLMM mappings were 1-1. That apparently
> changed some time ago, so with this patch the MPM consumers will actually
> be hooked up to the correct interrupt lines.
>
> Fixes: 59d34ca97f91 ("arm64: dts: qcom: Add initial device tree for SM6375")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
As agreed with Krzysztof offline, this one is a no-go.
Awaiting resolution on RPM MSG RAM bindings.
Konrad
> arch/arm64/boot/dts/qcom/sm6375.dtsi | 32 ++++++++++++++++++++++++++------
> 1 file changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> index 94bb373f8d97..ecb654357288 100644
> --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> @@ -315,6 +315,7 @@ CPU_PD7: power-domain-cpu7 {
>
> CLUSTER_PD: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> + power-domains = <&wakegic>;
> domain-idle-states = <&CLUSTER_SLEEP_0>;
> };
> };
> @@ -633,7 +634,7 @@ tlmm: pinctrl@500000 {
> reg = <0 0x00500000 0 0x800000>;
> interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> gpio-ranges = <&tlmm 0 0 157>;
> - /* TODO: Hook up MPM as wakeup-parent when it's there */
> + wakeup-parent = <&wakegic>;
> interrupt-controller;
> gpio-controller;
> #interrupt-cells = <2>;
> @@ -755,7 +756,7 @@ spmi_bus: spmi@1c40000 {
> <0 0x01c0a000 0 0x26000>;
> reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> interrupt-names = "periph_irq";
> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>;
> qcom,ee = <0>;
> qcom,channel = <0>;
> #address-cells = <2>;
> @@ -791,6 +792,25 @@ rpm_msg_ram: sram@45f0000 {
> reg = <0 0x045f0000 0 0x7000>;
> };
>
> + wakegic: interrupt-controller@45f01b8 {
> + compatible = "qcom,mpm";
> + reg = <0 0x045f01b8 0 0x1000>;
> + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + #power-domain-cells = <0>;
> + interrupt-parent = <&intc>;
> + qcom,mpm-pin-count = <96>;
> + qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */
> + <12 422>, /* DWC3 ss_phy_irq */
> + <86 183>, /* MPM wake, SPMI */
> + <89 314>, /* TSENS0 0C */
> + <90 315>, /* TSENS1 0C */
> + <93 164>, /* DWC3 dm_hs_phy_irq */
> + <94 165>; /* DWC3 dp_hs_phy_irq */
> + };
> +
> sram@4690000 {
> compatible = "qcom,rpm-stats";
> reg = <0 0x04690000 0 0x400>;
> @@ -1185,10 +1205,10 @@ usb_1: usb@4ef8800 {
> <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> assigned-clock-rates = <19200000>, <133333333>;
>
> - interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> + <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>,
> + <&wakegic 93 IRQ_TYPE_LEVEL_HIGH>,
> + <&wakegic 94 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "hs_phy_irq",
> "ss_phy_irq",
> "dm_hs_phy_irq",
>
@@ -315,6 +315,7 @@ CPU_PD7: power-domain-cpu7 {
CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
+ power-domains = <&wakegic>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
};
@@ -633,7 +634,7 @@ tlmm: pinctrl@500000 {
reg = <0 0x00500000 0 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 157>;
- /* TODO: Hook up MPM as wakeup-parent when it's there */
+ wakeup-parent = <&wakegic>;
interrupt-controller;
gpio-controller;
#interrupt-cells = <2>;
@@ -755,7 +756,7 @@ spmi_bus: spmi@1c40000 {
<0 0x01c0a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&wakegic 86 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@@ -791,6 +792,25 @@ rpm_msg_ram: sram@45f0000 {
reg = <0 0x045f0000 0 0x7000>;
};
+ wakegic: interrupt-controller@45f01b8 {
+ compatible = "qcom,mpm";
+ reg = <0 0x045f01b8 0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #power-domain-cells = <0>;
+ interrupt-parent = <&intc>;
+ qcom,mpm-pin-count = <96>;
+ qcom,mpm-pin-map = <5 296>, /* Soundwire wake_irq */
+ <12 422>, /* DWC3 ss_phy_irq */
+ <86 183>, /* MPM wake, SPMI */
+ <89 314>, /* TSENS0 0C */
+ <90 315>, /* TSENS1 0C */
+ <93 164>, /* DWC3 dm_hs_phy_irq */
+ <94 165>; /* DWC3 dp_hs_phy_irq */
+ };
+
sram@4690000 {
compatible = "qcom,rpm-stats";
reg = <0 0x04690000 0 0x400>;
@@ -1185,10 +1205,10 @@ usb_1: usb@4ef8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <133333333>;
- interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <&wakegic 12 IRQ_TYPE_LEVEL_HIGH>,
+ <&wakegic 93 IRQ_TYPE_LEVEL_HIGH>,
+ <&wakegic 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq",
"ss_phy_irq",
"dm_hs_phy_irq",