Message ID | 20230302154724.856062-1-krzysztof.kozlowski@linaro.org |
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State | New |
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([178.197.216.144]) by smtp.gmail.com with ESMTPSA id u2-20020a50eac2000000b0049e1f167956sm9987edp.9.2023.03.02.07.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 07:47:27 -0800 (PST) From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> To: Andy Gross <agross@kernel.org>, Bjorn Andersson <andersson@kernel.org>, Konrad Dybcio <konrad.dybcio@linaro.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH] arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address Date: Thu, 2 Mar 2023 16:47:24 +0100 Message-Id: <20230302154724.856062-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759271866928624601?= X-GMAIL-MSGID: =?utf-8?q?1759271866928624601?= |
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arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address
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Commit Message
Krzysztof Kozlowski
March 2, 2023, 3:47 p.m. UTC
The second LPASS pin controller IO address is supposed to be the MCC
range which contains the slew rate registers. The Linux driver then
accesses slew rate register with hard-coded offset (0xa000). However
the DTS contained the address of slew rate register as the second IO
address, thus any reads were effectively pass the memory space and lead
to "Internal error: synchronous external aborts" when applying pin
configuration.
Fixes: 6de7f9c34358 ("arm64: dts: qcom: sm8550: add GPR and LPASS pin controller")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Fix for current cycle - v6.3-rc1.
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
On 02/03/2023 16:47, Krzysztof Kozlowski wrote: > The second LPASS pin controller IO address is supposed to be the MCC > range which contains the slew rate registers. The Linux driver then > accesses slew rate register with hard-coded offset (0xa000). However > the DTS contained the address of slew rate register as the second IO > address, thus any reads were effectively pass the memory space and lead > to "Internal error: synchronous external aborts" when applying pin > configuration. > > Fixes: 6de7f9c34358 ("arm64: dts: qcom: sm8550: add GPR and LPASS pin controller") > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Fix for current cycle - v6.3-rc1. > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 1dea055a6815..6296eb7adecd 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -2001,7 +2001,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP > lpass_tlmm: pinctrl@6e80000 { > compatible = "qcom,sm8550-lpass-lpi-pinctrl"; > reg = <0 0x06e80000 0 0x20000>, > - <0 0x0725a000 0 0x10000>; > + <0 0x07250000 0 0x10000>; > gpio-controller; > #gpio-cells = <2>; > gpio-ranges = <&lpass_tlmm 0 0 23>; Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Thu, 2 Mar 2023 16:47:24 +0100, Krzysztof Kozlowski wrote: > The second LPASS pin controller IO address is supposed to be the MCC > range which contains the slew rate registers. The Linux driver then > accesses slew rate register with hard-coded offset (0xa000). However > the DTS contained the address of slew rate register as the second IO > address, thus any reads were effectively pass the memory space and lead > to "Internal error: synchronous external aborts" when applying pin > configuration. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: sm8550: fix LPASS pinctrl slew base address commit: a5982b3971007161b423b39aa843bdb6713a9d44 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1dea055a6815..6296eb7adecd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2001,7 +2001,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP lpass_tlmm: pinctrl@6e80000 { compatible = "qcom,sm8550-lpass-lpi-pinctrl"; reg = <0 0x06e80000 0 0x20000>, - <0 0x0725a000 0 0x10000>; + <0 0x07250000 0 0x10000>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 23>;