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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS1PEPF0000E64E.mail.protection.outlook.com (10.167.18.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6156.12 via Frontend Transport; Wed, 1 Mar 2023 18:15:56 +0000 Received: from beas.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 1 Mar 2023 12:15:51 -0600 From: Wyes Karny To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , "Namhyung Kim" , Thomas Gleixner , "Borislav Petkov" , Dave Hansen , , Stephane Eranian , Oleksandr Natalenko CC: , , , , , Muhammad Usama Anjum , Wyes Karny Subject: [RFC PATCH v2 1/2] perf/x86/rapl: Fix energy-cores event Date: Wed, 1 Mar 2023 18:14:48 +0000 Message-ID: <20230301181449.14647-2-wyes.karny@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230301181449.14647-1-wyes.karny@amd.com> References: <20230301181449.14647-1-wyes.karny@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E64E:EE_|CH3PR12MB7739:EE_ X-MS-Office365-Filtering-Correlation-Id: 13389130-d14d-493e-c35a-08db1a8100db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2023 18:15:56.9781 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13389130-d14d-493e-c35a-08db1a8100db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E64E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7739 X-Spam-Status: No, score=-0.9 required=5.0 tests=BAYES_00,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759191269657962662?= X-GMAIL-MSGID: =?utf-8?q?1759191269657962662?= For quite some time, energy-cores event is broken, because RAPL PMU assumes all the events on this PMU are uncore and sets rapl_cpu_mask with the first available CPU on the die. Therefore, for energy-cores event if we read MSR form pmu->cpu, it's wrong. But the following two changes helped to hide this issue. - commit 704e2f5b700d ("perf stat: Use affinity for enabling/disabling events") - commit e64cd6f73ff5 ("perf/x86: Use PMUEF_READ_CPU_PKG in uncore events") These two changes together acted as a workaround for energy-cores event. First change affined perf events to respective CPUs whereas the second change helped to pick the local CPU to read the MSR. In this way, MSRs were read from the correct CPU. This works unless it's the first reading. For the first reading the second patch doesn't apply and we get wrong readings. Stephane reported this issue when a patch to enable AMD energy-cores RAPL event was posted [1]. The right way to fix the issue is to get rid of RAPL being considered an uncore event. That is a larger change. To enable current RAPL usage, work around the issue by conditionally remove the `PERF_EV_CAP_READ_ACTIVE_PKG` flag for energy-cores event. Also, use the event's CPU instead for PMU's CPU to read the MSR. [1]: https://lore.kernel.org/lkml/CABPqkBQ_bSTC-OEe_LrgUrpj2VsseX1ThvO-yLcEtF8vb4+AAw@mail.gmail.com/#t Fixes: e64cd6f73ff5 ("perf/x86: Use PMUEF_READ_CPU_PKG in uncore events") Signed-off-by: Wyes Karny --- arch/x86/events/rapl.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 52e6e7ed4f78..e6a0c077daf5 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -343,14 +343,15 @@ static int rapl_pmu_event_init(struct perf_event *event) if (event->cpu < 0) return -EINVAL; - event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; - if (!cfg || cfg >= NR_RAPL_DOMAINS + 1) return -EINVAL; cfg = array_index_nospec((long)cfg, NR_RAPL_DOMAINS + 1); bit = cfg - 1; + if (bit != PERF_RAPL_PP0) + event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; + /* check event supported */ if (!(rapl_cntr_mask & (1 << bit))) return -EINVAL; @@ -363,7 +364,15 @@ static int rapl_pmu_event_init(struct perf_event *event) pmu = cpu_to_rapl_pmu(event->cpu); if (!pmu) return -EINVAL; - event->cpu = pmu->cpu; + + /* + * FIXME: RAPL PMU considers events are uncore and MSRs can be read from + * the first available CPU of the die. But this is not true for energy-cores + * event. Therefore as a workaround don't consider pmu->cpu here for PERF_RAPL_PP0. + */ + if (event->event_caps & PERF_EV_CAP_READ_ACTIVE_PKG) + event->cpu = pmu->cpu; + event->pmu_private = pmu; event->hw.event_base = rapl_msrs[bit].msr; event->hw.config = cfg;