Message ID | 20230301002657.352637-3-Mr.Bossman075@gmail.com |
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State | New |
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[108.26.182.112]) by smtp.gmail.com with ESMTPSA id t8-20020ac85888000000b003bb8c60cdf1sm7576698qta.78.2023.02.28.16.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Feb 2023 16:27:00 -0800 (PST) From: Jesse Taube <mr.bossman075@gmail.com> X-Google-Original-From: Jesse Taube <Mr.Bossman075@gmail.com> To: linux-riscv@lists.infradead.org Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jesse Taube <Mr.Bossman075@gmail.com>, Yimin Gu <ustcymgu@gmail.com>, Damien Le Moal <damien.lemoal@wdc.com>, Stephen Boyd <sboyd@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Waldemar Brodkorb <wbx@openadk.org>, Albert Ou <aou@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com> Subject: [PATCH v3 2/3] riscv: Kconfig: Allow RV32 to build with no MMU Date: Tue, 28 Feb 2023 19:26:56 -0500 Message-Id: <20230301002657.352637-3-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230301002657.352637-1-Mr.Bossman075@gmail.com> References: <20230301002657.352637-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759123544430952573?= X-GMAIL-MSGID: =?utf-8?q?1759123544430952573?= |
Series |
Add RISC-V 32 NOMMU support
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Commit Message
Jesse T
March 1, 2023, 12:26 a.m. UTC
From: Yimin Gu <ustcymgu@gmail.com> Some RISC-V 32bit cores do not have an MMU, and the kernel should be able to build for them. This patch enables the RV32 to be built with no MMU support. Signed-off-by: Yimin Gu <ustcymgu@gmail.com> CC: Jesse Taube <Mr.Bossman075@gmail.com> Tested-by: Waldemar Brodkorb <wbx@openadk.org> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> --- V1->V2: - Fix typo in commit description V2->V3: - No change --- arch/riscv/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Comments
On 3/1/23 09:26, Jesse Taube wrote: > From: Yimin Gu <ustcymgu@gmail.com> > > Some RISC-V 32bit cores do not have an MMU, and the kernel should be > able to build for them. This patch enables the RV32 to be built with > no MMU support. > > Signed-off-by: Yimin Gu <ustcymgu@gmail.com> > CC: Jesse Taube <Mr.Bossman075@gmail.com> > Tested-by: Waldemar Brodkorb <wbx@openadk.org> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> Looks OK. Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c5e42cc37604..d1f661425790 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -177,8 +177,8 @@ config MMU config PAGE_OFFSET hex - default 0xC0000000 if 32BIT - default 0x80000000 if 64BIT && !MMU + default 0xC0000000 if 32BIT && MMU + default 0x80000000 if !MMU default 0xff60000000000000 if 64BIT config KASAN_SHADOW_OFFSET @@ -279,7 +279,6 @@ config ARCH_RV32I select GENERIC_LIB_ASHRDI3 select GENERIC_LIB_LSHRDI3 select GENERIC_LIB_UCMPDI2 - select MMU config ARCH_RV64I bool "RV64I"