From patchwork Mon Feb 27 22:29:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgecombe, Rick P" X-Patchwork-Id: 62177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2682855wrd; Mon, 27 Feb 2023 14:34:56 -0800 (PST) X-Google-Smtp-Source: AK7set9vr+bTO4YCY437WjABXiskXInhWhRa3NfmG+4TOomxQDwEAhyYzmkt+fjoxOP7YiuOIDth X-Received: by 2002:a17:907:a427:b0:8ab:a378:5f96 with SMTP id sg39-20020a170907a42700b008aba3785f96mr11731027ejc.3.1677537296682; Mon, 27 Feb 2023 14:34:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677537296; cv=none; d=google.com; s=arc-20160816; b=yJvMxd/6GimKALMp0kJGyoUCJMCMI/Ec66bJbt3X/A+fQ+ltD6gBFxMzcdWJ/IWzwE MBnOHoVUFXN+WzZqPhI8L4LFEi4zf2BOzQQHiQBA/+aJflc/2sTzGdxbUtXNz5lAIX6t usCCQBAFLWy7rwcAEXttVHkThvMMQKD6+EcwFfTV7b3mlVRrJYiZKA01I931zpZApZA3 ajX3z686M3kT2rzajXSiRajP6iRF5VS1CCKd1+OyihDNN6Bvz+/6/dwz99IolesWvEAe UcmtKCe2FvZwCEaZa4e8CvoJzpsNTNrlRkqNb0R2ILj4UKUIUhi3eep+3W9/TJ9VYiho Ssew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=MvWt7ReyhF/wn7NboBw5a1sJLt/UxAkay4sKp6Ow5WM=; b=DL1qT6MXQvpoUCzYH2hddIX6bDebHdy0MYuSdWAJGf53M45X9sm5+0LoAbJudcmaT4 1SRQlPY46CpxLskqqZ9+oKNuNix+bRk1CPjTi6I1sUbRhDUFV8pBc/rYjUfeaVNS8sJ1 6TMA2SrcL367AfT/YAhsEZfvmtw7eNTj0jafG7tjO15fY22NLbmjUZt1Ja71YylKHQnm HLz1PVDIqHusrDLdohlUqZFlKKvP5+MUcm7WtGyDrGaUrHgXwhE4Odyoe2h0C7rytVtZ rjmkCtXBV+zdSyV7S0gRUX+GcPRLvi2ex60Yn1FRR7e92ZkqDw2E2kue3Amvv+yYfY20 cTZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="D00v5Cw/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id by25-20020a0564021b1900b004accd446474si9203790edb.545.2023.02.27.14.34.31; Mon, 27 Feb 2023 14:34:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="D00v5Cw/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230280AbjB0Wc1 (ORCPT + 99 others); Mon, 27 Feb 2023 17:32:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230201AbjB0Wbh (ORCPT ); Mon, 27 Feb 2023 17:31:37 -0500 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 817E3298F0; Mon, 27 Feb 2023 14:31:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677537091; x=1709073091; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=D7r3sPYzuOicvyDyAiCcjJlcjrFZlOzlMPKscQsbvdA=; b=D00v5Cw/5/5Swn5WtRlN8Wc/Tvnp2pi2PmadrF0xeFldyaSNTUiC4mma ctjh5gzMvHmnNiH5gLjexWKh7kj1JIaQudKFLTKNbIK6sCx2oEUQKyAcg g1LUhBIO/ySzywfA+LCf0DKYwoVGnpjPe6qVpWuTQm7nLk/NnrwfF+3El P7PvrIwdMGbVv8F7hqCcTtWV1TW0tuq0LwWGVhpFvvRBiQnjzetZE9mz5 cFCBpfVnayYl+lN21ZSHTL+apWPHCJ4c4Tfzl/FAma5HdHi6UUczlXQjA Vj2rWVBX+P41QVu2hT1jyGmH1Gct62dp4+DPfR9d0IFhqh3RcELBlNxP0 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="313657127" X-IronPort-AV: E=Sophos;i="5.98,220,1673942400"; d="scan'208";a="313657127" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2023 14:31:12 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10634"; a="848024393" X-IronPort-AV: E=Sophos;i="5.98,220,1673942400"; d="scan'208";a="848024393" Received: from leonqu-mobl1.amr.corp.intel.com (HELO rpedgeco-desk.amr.corp.intel.com) ([10.209.72.19]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2023 14:31:11 -0800 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, david@redhat.com, debug@rivosinc.com Cc: rick.p.edgecombe@intel.com Subject: [PATCH v7 06/41] x86/fpu: Add helper for modifying xstate Date: Mon, 27 Feb 2023 14:29:22 -0800 Message-Id: <20230227222957.24501-7-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230227222957.24501-1-rick.p.edgecombe@intel.com> References: <20230227222957.24501-1-rick.p.edgecombe@intel.com> X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759025348112763487?= X-GMAIL-MSGID: =?utf-8?q?1759025348112763487?= Just like user xfeatures, supervisor xfeatures can be active in the registers or present in the task FPU buffer. If the registers are active, the registers can be modified directly. If the registers are not active, the modification must be performed on the task FPU buffer. When the state is not active, the kernel could perform modifications directly to the buffer. But in order for it to do that, it needs to know where in the buffer the specific state it wants to modify is located. Doing this is not robust against optimizations that compact the FPU buffer, as each access would require computing where in the buffer it is. The easiest way to modify supervisor xfeature data is to force restore the registers and write directly to the MSRs. Often times this is just fine anyway as the registers need to be restored before returning to userspace. Do this for now, leaving buffer writing optimizations for the future. Add a new function fpregs_lock_and_load() that can simultaneously call fpregs_lock() and do this restore. Also perform some extra sanity checks in this function since this will be used in non-fpu focused code. Tested-by: Pengfei Xu Tested-by: John Allen Tested-by: Kees Cook Acked-by: Mike Rapoport (IBM) Reviewed-by: Kees Cook Suggested-by: Thomas Gleixner Signed-off-by: Rick Edgecombe --- v6: - Drop "but appear to work" (Boris) v5: - Fix spelling error (Boris) - Don't export fpregs_lock_and_load() (Boris) v3: - Rename to fpregs_lock_and_load() to match the unlocking fpregs_unlock(). (Kees) - Elaborate in comment about helper. (Dave) v2: - Drop optimization of writing directly the buffer, and change API accordingly. - fpregs_lock_and_load() suggested by tglx - Some commit log verbiage from dhansen --- arch/x86/include/asm/fpu/api.h | 9 +++++++++ arch/x86/kernel/fpu/core.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index 503a577814b2..aadc6893dcaa 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -82,6 +82,15 @@ static inline void fpregs_unlock(void) preempt_enable(); } +/* + * FPU state gets lazily restored before returning to userspace. So when in the + * kernel, the valid FPU state may be kept in the buffer. This function will force + * restore all the fpu state to the registers early if needed, and lock them from + * being automatically saved/restored. Then FPU state can be modified safely in the + * registers, before unlocking with fpregs_unlock(). + */ +void fpregs_lock_and_load(void); + #ifdef CONFIG_X86_DEBUG_FPU extern void fpregs_assert_state_consistent(void); #else diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index caf33486dc5e..f851558b673f 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -753,6 +753,24 @@ void switch_fpu_return(void) } EXPORT_SYMBOL_GPL(switch_fpu_return); +void fpregs_lock_and_load(void) +{ + /* + * fpregs_lock() only disables preemption (mostly). So modifying state + * in an interrupt could screw up some in progress fpregs operation. + * Warn about it. + */ + WARN_ON_ONCE(!irq_fpu_usable()); + WARN_ON_ONCE(current->flags & PF_KTHREAD); + + fpregs_lock(); + + fpregs_assert_state_consistent(); + + if (test_thread_flag(TIF_NEED_FPU_LOAD)) + fpregs_restore_userregs(); +} + #ifdef CONFIG_X86_DEBUG_FPU /* * If current FPU state according to its tracking (loaded FPU context on this