diff mbox series

[v2,02/13] dt-bindings: PCI: qcom: Add iommu properties

Message ID 20230224105906.16540-3-manivannan.sadhasivam@linaro.org
State New
Headers
Series Add PCIe RC support to Qcom SDX55 SoC |

Commit Message

Manivannan Sadhasivam Feb. 24, 2023, 10:58 a.m. UTC 
  Most of the PCIe controllers require iommu support to function properly.
So let's add them to the binding.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Rob Herring Feb. 27, 2023, 7:55 p.m. UTC | #1 
On Fri, Feb 24, 2023 at 04:28:55PM +0530, Manivannan Sadhasivam wrote:
> Most of the PCIe controllers require iommu support to function properly.
> So let's add them to the binding.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index a3639920fcbb..f48d0792aa57 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -64,6 +64,11 @@ properties:
>  
>    dma-coherent: true
>  
> +  iommus:
> +    maxItems: 1
> +
> +  iommu-map: true
> +

I think both properties together doesn't make sense unless the PCI host 
itself does DMA in addition to PCI bus devices doing DMA.

Rob
Manivannan Sadhasivam Feb. 28, 2023, 8:20 a.m. UTC | #2 
On Mon, Feb 27, 2023 at 01:55:35PM -0600, Rob Herring wrote:
> On Fri, Feb 24, 2023 at 04:28:55PM +0530, Manivannan Sadhasivam wrote:
> > Most of the PCIe controllers require iommu support to function properly.
> > So let's add them to the binding.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > index a3639920fcbb..f48d0792aa57 100644
> > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > @@ -64,6 +64,11 @@ properties:
> >  
> >    dma-coherent: true
> >  
> > +  iommus:
> > +    maxItems: 1
> > +
> > +  iommu-map: true
> > +
> 
> I think both properties together doesn't make sense unless the PCI host 
> itself does DMA in addition to PCI bus devices doing DMA.
> 

How? With "iommus", we specify the SMR mask along with the starting SID and with
iommu-map, the individual SID<->BDF mapping is specified. This has nothing to
do with host DMA capabilities.

Thanks,
Mani

> Rob
Rob Herring March 1, 2023, 2:58 p.m. UTC | #3 
+Robin

On Tue, Feb 28, 2023 at 2:20 AM Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
>
> On Mon, Feb 27, 2023 at 01:55:35PM -0600, Rob Herring wrote:
> > On Fri, Feb 24, 2023 at 04:28:55PM +0530, Manivannan Sadhasivam wrote:
> > > Most of the PCIe controllers require iommu support to function properly.
> > > So let's add them to the binding.
> > >
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > >  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
> > >  1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > index a3639920fcbb..f48d0792aa57 100644
> > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > @@ -64,6 +64,11 @@ properties:
> > >
> > >    dma-coherent: true
> > >
> > > +  iommus:
> > > +    maxItems: 1
> > > +
> > > +  iommu-map: true
> > > +
> >
> > I think both properties together doesn't make sense unless the PCI host
> > itself does DMA in addition to PCI bus devices doing DMA.
> >
>
> How? With "iommus", we specify the SMR mask along with the starting SID and with
> iommu-map, the individual SID<->BDF mapping is specified. This has nothing to
> do with host DMA capabilities.

I spoke with Robin offline and he agrees that having both is broken at
least in RC mode. He pointed out the issue is similar to this one on
Tegra[1].

Rob

[1] https://lore.kernel.org/all/AS8P193MB2095640357779A7F9B6026F8D2A19@AS8P193MB2095.EURP193.PROD.OUTLOOK.COM/
Manivannan Sadhasivam March 8, 2023, 8 a.m. UTC | #4 
On Wed, Mar 01, 2023 at 08:58:51AM -0600, Rob Herring wrote:
> +Robin
> 
> On Tue, Feb 28, 2023 at 2:20 AM Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
> >
> > On Mon, Feb 27, 2023 at 01:55:35PM -0600, Rob Herring wrote:
> > > On Fri, Feb 24, 2023 at 04:28:55PM +0530, Manivannan Sadhasivam wrote:
> > > > Most of the PCIe controllers require iommu support to function properly.
> > > > So let's add them to the binding.
> > > >
> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 5 +++++
> > > >  1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > > index a3639920fcbb..f48d0792aa57 100644
> > > > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> > > > @@ -64,6 +64,11 @@ properties:
> > > >
> > > >    dma-coherent: true
> > > >
> > > > +  iommus:
> > > > +    maxItems: 1
> > > > +
> > > > +  iommu-map: true
> > > > +
> > >
> > > I think both properties together doesn't make sense unless the PCI host
> > > itself does DMA in addition to PCI bus devices doing DMA.
> > >
> >
> > How? With "iommus", we specify the SMR mask along with the starting SID and with
> > iommu-map, the individual SID<->BDF mapping is specified. This has nothing to
> > do with host DMA capabilities.
> 
> I spoke with Robin offline and he agrees that having both is broken at
> least in RC mode. He pointed out the issue is similar to this one on
> Tegra[1].
> 

Looked into that thread and concluded that "iommus" property should go away.
Submitted a patch [1] to remove that property from PCIe nodes of all Qualcomm
SoCs.

Thanks for pointing out! Will update this bindings patch in next revision.

- Mani

[1] https://lore.kernel.org/linux-arm-msm/20230308075648.134119-1-manivannan.sadhasivam@linaro.org/

> Rob
> 
> [1] https://lore.kernel.org/all/AS8P193MB2095640357779A7F9B6026F8D2A19@AS8P193MB2095.EURP193.PROD.OUTLOOK.COM/
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a3639920fcbb..f48d0792aa57 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -64,6 +64,11 @@  properties:
 
   dma-coherent: true
 
+  iommus:
+    maxItems: 1
+
+  iommu-map: true
+
   interconnects:
     maxItems: 2