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[v2,01/13] dt-bindings: PCI: qcom: Update maintainers entry

Message ID	20230224105906.16540-2-manivannan.sadhasivam@linaro.org
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Subject: [PATCH v2 01/13] dt-bindings: PCI: qcom: Update maintainers entry Date: Fri, 24 Feb 2023 16:28:54 +0530 Message-Id: <20230224105906.16540-2-manivannan.sadhasivam@linaro.org> In-Reply-To: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> References: <20230224105906.16540-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add PCIe RC support to Qcom SDX55 SoC \| [v2,00/13] Add PCIe RC support to Qcom SDX55 SoC [v2,01/13] dt-bindings: PCI: qcom: Update maintainers entry [v2,02/13] dt-bindings: PCI: qcom: Add iommu properties [v2,03/13] dt-bindings: PCI: qcom: Add SDX55 SoC [v2,04/13] dt-bindings: PCI: qcom-ep: Fix the unit address used in example [v2,05/13] ARM: dts: qcom: sdx55: Fix the unit address of PCIe EP node [v2,06/13] ARM: dts: qcom: sdx55: Rename pcie0_{phy/lane} to pcie_{phy/lane} [v2,07/13] ARM: dts: qcom: sdx55: Add support for PCIe RC controller [v2,08/13] ARM: dts: qcom: sdx55: List the property values vertically [v2,09/13] ARM: dts: qcom: sdx55-t55: Enable PCIe RC support [v2,10/13] ARM: dts: qcom: sdx55-t55: Move "status" property down [v2,11/13] phy: qcom-qmp-pcie: Split out EP related init sequence for SDX55 [v2,12/13] phy: qcom-qmp-pcie: Add RC init sequence for SDX55 [v2,13/13] PCI: qcom: Add support for SDX55 SoC

Commit Message

Manivannan Sadhasivam Feb. 24, 2023, 10:58 a.m. UTC

  Stan is no longer working with MMSOL and expressed his interest to not
continue maintaining Qcom PCIe driver. Since I took over the driver
maintainership, I'm stepping in to maintain the binding also.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index a5859bb3dc28..a3639920fcbb 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -8,7 +8,7 @@  title: Qualcomm PCI express root complex
 
 maintainers:
   - Bjorn Andersson <bjorn.andersson@linaro.org>
-  - Stanimir Varbanov <svarbanov@mm-sol.com>
+  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
 
 description: |
   Qualcomm PCIe root complex controller is based on the Synopsys DesignWare