From patchwork Fri Feb 24 07:01:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 61149 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp756161wrd; Thu, 23 Feb 2023 23:29:15 -0800 (PST) X-Google-Smtp-Source: AK7set+uHqJm/FKHjJGXlDAvZKH4zNRifCf680FgCZhhGSlqeg7haNyI6H3sjTbJOdwNoHEMadsC X-Received: by 2002:aa7:cd77:0:b0:4ac:b69a:2f06 with SMTP id ca23-20020aa7cd77000000b004acb69a2f06mr15708095edb.0.1677223754825; Thu, 23 Feb 2023 23:29:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677223754; cv=none; d=google.com; s=arc-20160816; b=O17IQpnGxtRoHuPXLaI9JvjYHK3KzfTmWrTZFptIee9jTfARtyQRcZSVG1ku3HotfL BePAlqxWfk/WIwkJMbpKMZSJDei4YpQo7O7ji8NSosNxJvvn6Jpb14rz+0Se7yHcaSzb Y9WNhz94oLfa3p3xh0owJVonIOakklCtXwqKuwVnFh9yHT3KFWB2TEFQmKmXeg9jJOcz 7PfjX2YAsQg6/vZ2A5GQPeQ4uFDonX31liar6kDE7QCTSkpWZKvhDkgQzkzSAjGnZMx+ VUkv+UcxDp8W6pggvaDtcOth9arugqGQ7HjAHHopZr5cJxe7ATZqunvOl9e+hlZEtBDW ULRA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ay703HfwKyfkyz4I6BpIuXD4Ka9Ste1+E4ewnIA8uUo=; b=TfRYFf7Te7PjH8LxIj3VH+fR+T00HCTfsdq3/zhyzeGdUEW549TlYE8GfFafQDaadr ickUBeGDynVHsaOENUKHV7xmHKJXjTsSiYHCdWrA8drZ/4F2MiapgefvloVEYTOEWv6w jehUygDDZnW4oM+R3R1S3oObXaFpfnqSB135D6UesmdIOcv5ygV3pgl2NttsSiMqgb0B U2gt1gmDfq/b2j8cyl3NwcfRHMonoygGx2M7z5DH/Sypph6W63Mz2mf8zNJSXxMKaudE cGuuAke7rRCtwgkfqC+IEyzKvyTWyo24H/9QO3cf5kuFJMQQZmOO/DWGFqBPIQhzEHPi tO/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=j7ypfV3L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id n19-20020aa7d053000000b004ab250bcee4si6511665edo.646.2023.02.23.23.28.51; Thu, 23 Feb 2023 23:29:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=j7ypfV3L; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229720AbjBXH2V (ORCPT + 99 others); Fri, 24 Feb 2023 02:28:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229606AbjBXH2A (ORCPT ); Fri, 24 Feb 2023 02:28:00 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35C9F7EC3; Thu, 23 Feb 2023 23:27:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677223675; x=1708759675; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uSGLCwu5a/GZ7qpPDjOQ37bzlx0va0P3TMBnImGGqAs=; b=j7ypfV3L9YakMAbe2khYbWNuRTfmlVZB427LsGB6fCJncJjUsKISBeHW j69OLXhRY/Mrmo4bKoUgMCiJPQFgozD5oQeSIgMNGqRLBPQtgll4AlJFK P9ORwpktcjkl8cOqzSSBaydm6tttKWRYonUlm4vR/j7bEjeZgnNpomQmj +h1/zcdKyqjIMzpaNDjobVqd/ge9UEeqCNjp87U5T6ou5Y2CwDe3OTZ0f hguTGGI7vcdxsL12vEflZo9uBF22IthZUaGKId/YLWjis8SwAsyV+oi3v mmZUNTtvjtiudUpzYBZ3jjbllp83miPiGY9cokdg8J30233trLmieEZC3 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="334835967" X-IronPort-AV: E=Sophos;i="5.97,324,1669104000"; d="scan'208";a="334835967" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 23:27:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="815639203" X-IronPort-AV: E=Sophos;i="5.97,324,1669104000"; d="scan'208";a="815639203" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga001.fm.intel.com with ESMTP; 23 Feb 2023 23:27:20 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [RFC PATCH v3 06/32] x86/cpufeature: add the cpu feature bit for FRED Date: Thu, 23 Feb 2023 23:01:19 -0800 Message-Id: <20230224070145.3572-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230224070145.3572-1-xin3.li@intel.com> References: <20230224070145.3572-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758696576250260371?= X-GMAIL-MSGID: =?utf-8?q?1758696576250260371?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for FRED (Flexible Return and Event Delivery). The Intel flexible return and event delivery (FRED) architecture defines simple new transitions that change privilege level (ring transitions). The FRED architecture was designed with the following goals: 1) Improve overall performance and response time by replacing event delivery through the interrupt descriptor table (IDT event delivery) and event return by the IRET instruction with lower latency transitions. 2) Improve software robustness by ensuring that event delivery establishes the full supervisor context and that event return establishes the full user context. The new transitions defined by the FRED architecture are FRED event delivery and, for returning from events, two FRED return instructions. FRED event delivery can effect a transition from ring 3 to ring 0, but it is used also to deliver events incident to ring 0. One FRED instruction (ERETU) effects a return from ring 0 to ring 3, while the other (ERETS) returns while remaining in ring 0. Search for the latest FRED spec in most search engines with this search pattern: site:intel.com FRED (flexible return and event delivery) specification Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index fdb8e09234ba..ef6e638fa300 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -315,6 +315,7 @@ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ #define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* "" Intel Architectural PerfMon Extension */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index b70111a75688..b2218a7a0927 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -312,6 +312,7 @@ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ #define X86_FEATURE_CMPCCXADD (12*32+ 7) /* "" CMPccXADD instructions */ +#define X86_FEATURE_FRED (12*32+17) /* Flexible Return and Event Delivery */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */