From patchwork Fri Feb 24 07:01:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 61154 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp756323wrd; Thu, 23 Feb 2023 23:29:47 -0800 (PST) X-Google-Smtp-Source: AK7set+ve3jo7Y5fJDYO1NfIboON39OlnBbjbiVDTjc5ub8Tky4lKBS3uR2oO4HIW6HTt9wfVsCW X-Received: by 2002:a50:ee01:0:b0:4ae:eb0f:892e with SMTP id g1-20020a50ee01000000b004aeeb0f892emr13876150eds.20.1677223787071; Thu, 23 Feb 2023 23:29:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677223787; cv=none; d=google.com; s=arc-20160816; b=Vlbhty3z5/ZcXVaUKfd0VOXFeXWO8+q9Td+Wqxhjx31qXxVDm82n9qVSCAur2ycyVy LV2EJoMnRqQMI2uJVeoUijcI5JmFQDgxI68QWBOvFw0ex5HqdeChjPwXzm+8H2LvvwvU xBIwPYfuhTDL47CTtwrwFM4EsLLRXPKs+Wm+ha2OXIgWrzDMlYvcglq8nbb6oRjHuk7D C3npcaTJdfsFLqhJ8CwnHw/oB3GDFaSIkBzy4/x/utvMWiBwYIFlUTbREz/R+oIi/UwC +z8DKI4xcnf+YLC0V4W5bfYwCPzelcr2XxtCNSgO+xfRZZi9J0QPJ1w4YPjArPQ+V1zn IRCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Fm3tON1dDM6h9S0umZ3Fr2nGbZxhT02mpLsg54uIPms=; b=dUnHNq0h3RPruNjkeZO/iB5XtaF7IymLZtbUfpTsSSVy8ZTRG6xMHgALENiPPUMSQR nNZkwy9dY0InWcK+LNnuN0m7KT6SIzh8qz5fmUzq81ughg19898tlxutNn3XrRbCaCH1 tZaNplHvjjOe0jQSXWjRb/9VsMx4PHJ4oNC0S0+Id8wE2hZXDdVE3K2zLcrfDtj7Exxt bq3hXDeRryLSsKQgg1F2H0gQVmhuK7kapdUGL6o7CRaCD1loug07Mza0sjCaC1v6zCAT 2bFU6WCHb5ZDPOHH0evUliXAZxCpqyT7dUmSqp/cDnFdtsU8pxmH3owcPT+LjSB+VjTr uIlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=VQK15ErG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ca23-20020aa7cd77000000b004acbde66fbbsi14677494edb.144.2023.02.23.23.29.23; Thu, 23 Feb 2023 23:29:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=VQK15ErG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229985AbjBXH2i (ORCPT + 99 others); Fri, 24 Feb 2023 02:28:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229780AbjBXH2P (ORCPT ); Fri, 24 Feb 2023 02:28:15 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5978438017; Thu, 23 Feb 2023 23:28:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677223681; x=1708759681; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EBPvYb+gJfY5lBKAurDpvp1Pyt5VBU6XG/KB8jZzGbc=; b=VQK15ErGdmMiHujHAsXNoFGznpQIvOquNQXWO4VN6IONs7l2UJ1tz+oU HajXgcNZrnKY2NGOIQ0kitfdzHQwb0uGpXYGRE/B8UWusKzucQrxZPy3w kCtNfqL2ah2w7i+/h8fF5mRMlyRrQcyba5sbpHwv+2V7he7Q2x8qjYrYP V18ArbCSAD7W7VB/FnFdAPt9EkV7Zr8r2N5L8xpNSWQdS/RxYH42elT9E qGBTgcYDQ5z3TtW1IvXC7tEtCnhEmINWfnEXItc02UKcqSxPGKttSQdbS BNZmpCT9jTbH4b87bOD6O0QbyHHc26Gfdo2a1pDKDtoSBBygdq9VeJNcp A==; X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="334836020" X-IronPort-AV: E=Sophos;i="5.97,324,1669104000"; d="scan'208";a="334836020" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2023 23:27:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10630"; a="815639222" X-IronPort-AV: E=Sophos;i="5.97,324,1669104000"; d="scan'208";a="815639222" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga001.fm.intel.com with ESMTP; 23 Feb 2023 23:27:22 -0800 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, andrew.cooper3@citrix.com, seanjc@google.com, pbonzini@redhat.com, ravi.v.shankar@intel.com Subject: [RFC PATCH v3 12/32] x86/cpu: add MSR numbers for FRED configuration Date: Thu, 23 Feb 2023 23:01:25 -0800 Message-Id: <20230224070145.3572-13-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230224070145.3572-1-xin3.li@intel.com> References: <20230224070145.3572-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758696610130660545?= X-GMAIL-MSGID: =?utf-8?q?1758696610130660545?= From: "H. Peter Anvin (Intel)" Add MSR numbers for the FRED configuration registers. Originally-by: Megha Dey Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/include/asm/msr-index.h | 13 ++++++++++++- tools/arch/x86/include/asm/msr-index.h | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ad35355ee43e..87db728f8bbc 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -36,8 +36,19 @@ #define EFER_FFXSR (1<<_EFER_FFXSR) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) -/* Intel MSRs. Some also available on other CPUs */ +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ +/* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL 0x00000033 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 37ff47552bcb..0ade66db3627 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -34,8 +34,19 @@ #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) -/* Intel MSRs. Some also available on other CPUs */ +/* FRED MSRs */ +#define MSR_IA32_FRED_RSP0 0x1cc /* Level 0 stack pointer */ +#define MSR_IA32_FRED_RSP1 0x1cd /* Level 1 stack pointer */ +#define MSR_IA32_FRED_RSP2 0x1ce /* Level 2 stack pointer */ +#define MSR_IA32_FRED_RSP3 0x1cf /* Level 3 stack pointer */ +#define MSR_IA32_FRED_STKLVLS 0x1d0 /* Exception stack levels */ +#define MSR_IA32_FRED_SSP0 MSR_IA32_PL0_SSP /* Level 0 shadow stack pointer */ +#define MSR_IA32_FRED_SSP1 0x1d1 /* Level 1 shadow stack pointer */ +#define MSR_IA32_FRED_SSP2 0x1d2 /* Level 2 shadow stack pointer */ +#define MSR_IA32_FRED_SSP3 0x1d3 /* Level 3 shadow stack pointer */ +#define MSR_IA32_FRED_CONFIG 0x1d4 /* Entrypoint and interrupt stack level */ +/* Intel MSRs. Some also available on other CPUs */ #define MSR_TEST_CTRL 0x00000033 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT 29 #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)