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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p8-20020a056402074800b004af65fa8733si3840168edy.113.2023.02.23.07.02.52; Thu, 23 Feb 2023 07:03:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=hDuVc56t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234671AbjBWOyq (ORCPT + 99 others); Thu, 23 Feb 2023 09:54:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234306AbjBWOyi (ORCPT ); Thu, 23 Feb 2023 09:54:38 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B15952DE6; Thu, 23 Feb 2023 06:54:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BCEE06602218; Thu, 23 Feb 2023 14:54:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1677164076; bh=2FDlNqFMvv568OceJDLOHaVPuNkoQcOewFS48O2E3K8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hDuVc56t9YVqQsWw8Z293SKRKZ++z7sXiXURKBM0uIr8fSXw2qoC0Flal9G2n9Bcg SJlLEncNL/dQTjNkoAB0Qt+TbHNsxdhXxzPkWqHT5LNMdaIStRygUpMt9pGEU2K0qH GX/rEaCMSNZZrP+4LW1dvGsAazCto1QUVBQrkGKm6n833DL1oN5pKUtODo9/CQfhDX eA/DBDYqicqHknC5cwT0n7F+sRhsU+PFKKUiIAyKGaKGJ88BVhQ11nuFdcPPX6HXf9 QwYGebToYhxPkP0bV1voaQDykZpFsLMF5eVw67S91vtBG+WPaobCGd+ng9l+NX22Qb u31Q5TMDaTu5w== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, AngeloGioacchino Del Regno Subject: [PATCH v1 3/4] arm64: dts: mediatek: mt8195: Add display pwm nodes Date: Thu, 23 Feb 2023 15:54:25 +0100 Message-Id: <20230223145426.193590-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230223145426.193590-1-angelogioacchino.delregno@collabora.com> References: <20230223145426.193590-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758634551017659835?= X-GMAIL-MSGID: =?utf-8?q?1758634551017659835?= Add the two hardware PWMs for display backlighting but keep them disabled by default, as usage is board-specific. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index fecb41104193..c86c4b48dc3f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1102,6 +1102,29 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; }; + disp_pwm0: pwm@1100e000 { + compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM0>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + disp_pwm1: pwm@1100f000 { + compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + interrupts = ; + #pwm-cells = <2>; + clocks = <&topckgen CLK_TOP_DISP_PWM1>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; + clock-names = "main", "mm"; + status = "disabled"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi";