diff mbox series

[v1,3/4] arm64: dts: mediatek: mt8195: Add display pwm nodes

Message ID 20230223145426.193590-4-angelogioacchino.delregno@collabora.com
State New
Headers
Series MT8195 Cherry: Enable PCIe/WiFi, add PWMs |

Commit Message

AngeloGioacchino Del Regno Feb. 23, 2023, 2:54 p.m. UTC 
  Add the two hardware PWMs for display backlighting but keep them
disabled by default, as usage is board-specific.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Chen-Yu Tsai Feb. 24, 2023, 9:01 a.m. UTC | #1 
On Thu, Feb 23, 2023 at 10:56 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Add the two hardware PWMs for display backlighting but keep them
> disabled by default, as usage is board-specific.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

and

Tested-by: Chen-Yu Tsai <wenst@chromium.org>

for disp_pwm0
Matthias Brugger March 31, 2023, 10:39 a.m. UTC | #2 
On 24/02/2023 10:01, Chen-Yu Tsai wrote:
> On Thu, Feb 23, 2023 at 10:56 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Add the two hardware PWMs for display backlighting but keep them
>> disabled by default, as usage is board-specific.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> 
> and
> 
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> 
> for disp_pwm0

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index fecb41104193..c86c4b48dc3f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1102,6 +1102,29 @@  lvts_ap: thermal-sensor@1100b000 {
 			#thermal-sensor-cells = <1>;
 		};
 
+		disp_pwm0: pwm@1100e000 {
+			compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM0>,
+				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
+		disp_pwm1: pwm@1100f000 {
+			compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100f000 0 0x1000>;
+			interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM1>,
+				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8195-spi",
 				     "mediatek,mt6765-spi";