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([85.235.12.219]) by smtp.gmail.com with ESMTPSA id y14-20020ac24e6e000000b004dc48d91061sm772238lfs.304.2023.02.23.05.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Feb 2023 05:32:55 -0800 (PST) From: Linus Walleij To: linux-kernel@vger.kernel.org, Greg Kroah-Hartman , Arnd Bergmann Cc: Linus Walleij , linux-gpio@vger.kernel.org, Marc Zyngier Subject: [PATCH] misc: microchip: pci1xxxx: Convert to immutable irqchip Date: Thu, 23 Feb 2023 14:32:52 +0100 Message-Id: <20230223133252.2257276-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758629169895107004?= X-GMAIL-MSGID: =?utf-8?q?1758629169895107004?= Convert the driver to immutable irq-chip with a bit of intuition. Cc: linux-gpio@vger.kernel.org Cc: Marc Zyngier Signed-off-by: Linus Walleij Acked-by: Marc Zyngier --- Maybe this would have been caught in review if the GPIO maintainers were involved, but the process isn't perfect. Better to just fix it. --- drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c index 3389803cb281..e616e3ec2b42 100644 --- a/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c +++ b/drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c @@ -175,9 +175,13 @@ static void pci1xxxx_gpio_irq_set_mask(struct irq_data *data, bool set) unsigned int gpio = irqd_to_hwirq(data); unsigned long flags; + if (!set) + gpiochip_enable_irq(chip, gpio); spin_lock_irqsave(&priv->lock, flags); pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set); spin_unlock_irqrestore(&priv->lock, flags); + if (set) + gpiochip_disable_irq(chip, gpio); } static void pci1xxxx_gpio_irq_mask(struct irq_data *data) @@ -283,12 +287,14 @@ static irqreturn_t pci1xxxx_gpio_irq_handler(int irq, void *dev_id) return IRQ_HANDLED; } -static struct irq_chip pci1xxxx_gpio_irqchip = { +static const struct irq_chip pci1xxxx_gpio_irqchip = { .name = "pci1xxxx_gpio", .irq_ack = pci1xxxx_gpio_irq_ack, .irq_mask = pci1xxxx_gpio_irq_mask, .irq_unmask = pci1xxxx_gpio_irq_unmask, .irq_set_type = pci1xxxx_gpio_set_type, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, }; static int pci1xxxx_gpio_suspend(struct device *dev) @@ -351,7 +357,7 @@ static int pci1xxxx_gpio_setup(struct pci1xxxx_gpio *priv, int irq) return retval; girq = &priv->gpio.irq; - girq->chip = &pci1xxxx_gpio_irqchip; + gpio_irq_chip_set_chip(girq, &pci1xxxx_gpio_irqchip); girq->parent_handler = NULL; girq->num_parents = 0; girq->parents = NULL;