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Peter Anvin" Subject: [PATCH v3 02/12] x86/mtrr: optimize mtrr_calc_physbits() Date: Thu, 23 Feb 2023 10:32:33 +0100 Message-Id: <20230223093243.1180-3-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230223093243.1180-1-jgross@suse.com> References: <20230223093243.1180-1-jgross@suse.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758614388222031474?= X-GMAIL-MSGID: =?utf-8?q?1758614388222031474?= Optimize mtrr_calc_physbits() for better readability. Drop a stale comment, as reality has made it obsolete. Signed-off-by: Juergen Gross --- V3: - new patch, split off from previous patch (Boris Petkov) --- arch/x86/kernel/cpu/mtrr/mtrr.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c index 8310bdb111d0..7596ebeab929 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -619,8 +619,6 @@ static struct syscore_ops mtrr_syscore_ops = { int __initdata changed_by_mtrr_cleanup; -#define SIZE_OR_MASK_BITS(n) (~((1ULL << ((n) - PAGE_SHIFT)) - 1)) - static unsigned int __init mtrr_calc_physbits(bool generic) { unsigned int phys_addr; @@ -628,15 +626,8 @@ static unsigned int __init mtrr_calc_physbits(bool generic) phys_addr = 32; if (generic) { - size_or_mask = SIZE_OR_MASK_BITS(36); - size_and_mask = 0x00f00000; phys_addr = 36; - /* - * This is an AMD specific MSR, but we assume(hope?) that - * Intel will implement it too when they extend the address - * bus of the Xeon. - */ if (cpuid_eax(0x80000000) >= 0x80000008) { phys_addr = cpuid_eax(0x80000008) & 0xff; /* CPUID workaround for Intel 0F33/0F34 CPU */ @@ -647,23 +638,19 @@ static unsigned int __init mtrr_calc_physbits(bool generic) boot_cpu_data.x86_stepping == 0x4)) phys_addr = 36; - size_or_mask = SIZE_OR_MASK_BITS(phys_addr); - size_and_mask = ~size_or_mask & 0xfffff00000ULL; } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR && boot_cpu_data.x86 == 6) { /* * VIA C* family have Intel style MTRRs, * but don't support PAE */ - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; phys_addr = 32; } - } else { - size_or_mask = SIZE_OR_MASK_BITS(32); - size_and_mask = 0; } + size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1); + size_and_mask = ~size_or_mask & 0xfffff00000ULL; + return phys_addr; }