From patchwork Thu Feb 23 06:27:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Tu X-Patchwork-Id: 60801 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp166881wrd; Wed, 22 Feb 2023 22:47:57 -0800 (PST) X-Google-Smtp-Source: AK7set91Eo+b8fNp1CO0DXUqTwsVKbclX6AVPCIPmChPgXqjxnIvmcqxkXFxF5iJEhVyvkPsSrKv X-Received: by 2002:a17:90b:30b:b0:234:b170:1f27 with SMTP id ay11-20020a17090b030b00b00234b1701f27mr10608062pjb.0.1677134877462; Wed, 22 Feb 2023 22:47:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677134877; cv=none; d=google.com; s=arc-20160816; b=t7G9utUku8B59Tlfw1HCNcmNRb5MmYHyEdBYlh2jzQrbjnUnvuVojRxdnZ2FEdU1Gy tM1rF7Mb3BR3SLSyfvT5xHkd0UZEut+D+CnjB/kbkRvh6cmbzvPVzJ5IONgHa5gjV3TT MOtS1p3Xy5BaemQmFvVN/Q16glIE7R8bC8OjN2Bx24wJ8nsO3Bwpmt7Zt2gm92XPaFnG KSQesmgegAKjG4GNE5fiOHULkcsxtntqBwKst8Yw2EBu7z+7eFBVDaUY9ajfU/O9EjSF ZqG+qXBivvHf7Bbbhs+tUW+K/zA11PyaVYmRLHyXPQPNK4ienAuPwhF26oAFjOYrqBUi Hbcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=Rw1M6GQR70u55nVSzWvenphKpxkh/2G6ZnhVgyvZ8wM=; b=CsPchpy7tAqcLXjnz+KzN4tc5IxJ+hR32Jh16srp+O6pGuo3uKMVFE3hrOsfIHX5Hh 7RYmxbatRHOWGqSHKR1lpZDUvvV8tqH07DGqXghBAw7NAz3AdBZydyeNvPTz4NyzPZXx iUFazMaXxy76+54dObcpJlQiDOlmAbg/tkT+UOvbljXw297CzMOHYSg/uaor6KCS8/P8 bj16zLuEixKx24E9aMN/XyvlRnMjsmCKZ18x5vBHVWH8EK1+cC5nztxLvOQf3ZEkRPHs AJ7hwUR0PeZXQIa47rzeMCqC/9r8l3Zd60EXuLM02AGLhX2vI9TvKbuzzx7qNdV30jjY mSSg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j4-20020a635944000000b004fab1ea0112si5144734pgm.528.2023.02.22.22.47.43; Wed, 22 Feb 2023 22:47:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233382AbjBWGbr (ORCPT + 99 others); Thu, 23 Feb 2023 01:31:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232906AbjBWGbp (ORCPT ); Thu, 23 Feb 2023 01:31:45 -0500 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1BFA4A1D7; Wed, 22 Feb 2023 22:30:57 -0800 (PST) Received: from droid06.amlogic.com (10.18.11.248) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Thu, 23 Feb 2023 14:30:55 +0800 From: Yu Tu To: , , , , "Neil Armstrong" , Jerome Brunet , Kevin Hilman , Michael Turquette , Stephen Boyd , "Martin Blumenstingl" CC: , , Yu Tu Subject: [PATCH] clk: meson: vid-pll-div: added meson_vid_pll_div_ops support to enable vid_pll_div to meet clock setting requirements, especially for late chip Date: Thu, 23 Feb 2023 14:27:23 +0800 Message-ID: <20230223062723.4770-1-yu.tu@amlogic.com> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Originating-IP: [10.18.11.248] X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758603381108494979?= X-GMAIL-MSGID: =?utf-8?q?1758603381108494979?= The previous chip only provides "ro_ops" for the vid_pll_div clock, which is not satisfied with the operation requirements of the later chip for this clock, so the ops that can be set for the clock is added. Signed-off-by: Yu Tu --- drivers/clk/meson/vid-pll-div.c | 59 +++++++++++++++++++++++++++++++++ drivers/clk/meson/vid-pll-div.h | 1 + 2 files changed, 60 insertions(+) base-commit: 8a9fbf00acfeeeaac8efab8091bb464bd71b70ea diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-div.c index daff235bc763..e75fa6f75efe 100644 --- a/drivers/clk/meson/vid-pll-div.c +++ b/drivers/clk/meson/vid-pll-div.c @@ -89,6 +89,65 @@ static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider); } +static int meson_vid_pll_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + unsigned long best = 0, now = 0; + unsigned int i, best_i = 0; + + for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) { + now = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate * + vid_pll_div_table[i].multiplier, + vid_pll_div_table[i].divider); + if (req->rate == now) { + return 0; + } else if (abs(now - req->rate) < abs(best - req->rate)) { + best = now; + best_i = i; + } + } + + if (best_i < ARRAY_SIZE(vid_pll_div_table)) + req->rate = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate * + vid_pll_div_table[best_i].multiplier, + vid_pll_div_table[best_i].divider); + else + req->rate = meson_vid_pll_div_recalc_rate(hw, req->best_parent_rate); + + return 0; +} + +static int meson_vid_pll_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk); + int i; + + for (i = 0 ; i < ARRAY_SIZE(vid_pll_div_table) ; ++i) { + if (DIV_ROUND_CLOSEST_ULL(parent_rate * vid_pll_div_table[i].multiplier, + vid_pll_div_table[i].divider) == rate) { + meson_parm_write(clk->map, &pll_div->val, vid_pll_div_table[i].shift_val); + meson_parm_write(clk->map, &pll_div->sel, vid_pll_div_table[i].shift_sel); + break; + } + } + + if (i >= ARRAY_SIZE(vid_pll_div_table)) { + pr_debug("%s: Invalid rate value for vid_pll_div\n", __func__); + return -EINVAL; + } + + return 0; +} + +const struct clk_ops meson_vid_pll_div_ops = { + .recalc_rate = meson_vid_pll_div_recalc_rate, + .determine_rate = meson_vid_pll_div_determine_rate, + .set_rate = meson_vid_pll_div_set_rate, +}; +EXPORT_SYMBOL_GPL(meson_vid_pll_div_ops); + const struct clk_ops meson_vid_pll_div_ro_ops = { .recalc_rate = meson_vid_pll_div_recalc_rate, }; diff --git a/drivers/clk/meson/vid-pll-div.h b/drivers/clk/meson/vid-pll-div.h index c0128e33ccf9..3ab729b85fde 100644 --- a/drivers/clk/meson/vid-pll-div.h +++ b/drivers/clk/meson/vid-pll-div.h @@ -16,5 +16,6 @@ struct meson_vid_pll_div_data { }; extern const struct clk_ops meson_vid_pll_div_ro_ops; +extern const struct clk_ops meson_vid_pll_div_ops; #endif /* __MESON_VID_PLL_DIV_H */