Update alderlake perf json from v1.18 to v1.19.
Based on:
https://github.com/intel/perfmon/pull/58
perf json files created using:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/alderlake/memory.json | 8 ++++++++
tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 10 ++++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
3 files changed, 19 insertions(+), 1 deletion(-)
@@ -24,6 +24,14 @@
"UMask": "0xf4",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.L1_MISS_AT_RET",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x81",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"EventCode": "0x05",
@@ -361,6 +361,16 @@
"UMask": "0xeb",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.INDIRECT",
+ "PEBS": "1",
+ "PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x80",
+ "Unit": "cpu_core"
+ },
{
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
"EventCode": "0xc5",
@@ -1,5 +1,5 @@
Family-model,Version,Filename,EventType
-GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core
+GenuineIntel-6-(97|9A|B7|BA|BF),v1.19,alderlake,core
GenuineIntel-6-BE,v1.18,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core