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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l5-20020a170907914500b008b1814ec83fsi17650302ejs.176.2023.02.22.07.36.17; Wed, 22 Feb 2023 07:36:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sRUZyKJQ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232594AbjBVPeT (ORCPT + 99 others); Wed, 22 Feb 2023 10:34:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232573AbjBVPeQ (ORCPT ); Wed, 22 Feb 2023 10:34:16 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1C8E38E9A for ; Wed, 22 Feb 2023 07:33:42 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id u10so9354609pjc.5 for ; Wed, 22 Feb 2023 07:33:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=frPAbJX6IbYMGdSO5i2vVIONplrg4szzCvfObYpFa4I=; b=sRUZyKJQWOKpCgL+u2PLfeiXYXt6xtXxNx+mTGh5sCovfq8lREW2rnC8ltuf5B17fs 9l6/lwqKLjHge+jOoPSKN1IM6oPrt4PJ2J9qqv/bDh3suh+ttLL4TnN7q4l/4MsdtwQH ytPWyWMG0HA84+N9GN9Rbd4Y6UM/6bjJkzUeHfnnWRUauPa/0WLdevWKceCqBOUeA4OZ ScvKoVW11YSjGxbS784ux4MPPaTbGmubJEULo8TzWCgVqJKuKacuHteWF5R02sPm0jRt +AiDe8iFAQHAiYZrnIeioPORCKGjWH3yeobUUgLFaeJSLZoPqQucAePclTimYwHQx3bb YADw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=frPAbJX6IbYMGdSO5i2vVIONplrg4szzCvfObYpFa4I=; b=FiXfs0AfbLgQDuCpVTXPJKelb1iUbOEAUCsFCFk9AC7o7opqkaui6NzZ1EYzuFCHuD SrLgdijkdKbL7HpMVRsn7OhBrRoBuWjFkLV3EAfMKwGcjzCoaSWNoNhXdWqxcRkdCVsh GMXOyLkjmj0Dl9mI5Esg6dgbs+TW6SabE/WgnsYjvt/E6vpW1OE238JN/nzhzQ6Tjn/A wPXfVXW9H0/mKMtm+JVgfnWllFVAMqVMw8pO/dg/4QUtEIdkrNYMfSoJiHCcy0u8nPVY IjwlXJbu3R3mal8SzftFtiJ5CNiE5y4K3wWwVpHp8tN4j244T3/Q43ZFe4h+92+0zoi8 fQvw== X-Gm-Message-State: AO0yUKU1HmrngxbKKhKPBs+1QaRWUrcOr/+ALQf1JqRHRdJRskg/RHMw Apc9tgXwp4BJT/BHkuTBASkk X-Received: by 2002:a05:6a20:a02a:b0:bc:d6e0:3ff6 with SMTP id p42-20020a056a20a02a00b000bcd6e03ff6mr10009690pzj.52.1677080020854; Wed, 22 Feb 2023 07:33:40 -0800 (PST) Received: from localhost.localdomain ([117.216.123.15]) by smtp.gmail.com with ESMTPSA id f15-20020aa78b0f000000b005ac419804d3sm5222482pfd.186.2023.02.22.07.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Feb 2023 07:33:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, robh@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org Cc: konrad.dybcio@linaro.org, bhelgaas@google.com, kishon@kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 07/11] ARM: dts: qcom: sdx55: Add support for PCIe RC controller Date: Wed, 22 Feb 2023 21:02:47 +0530 Message-Id: <20230222153251.254492-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230222153251.254492-1-manivannan.sadhasivam@linaro.org> References: <20230222153251.254492-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758546048875207986?= X-GMAIL-MSGID: =?utf-8?q?1758546048875207986?= The PCIe controller in SDX55 can act as the RC controller also. Let's add support for it. Signed-off-by: Manivannan Sadhasivam --- arch/arm/boot/dts/qcom-sdx55.dtsi | 72 +++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index a1f4a7b0904a..768d7d7f6335 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -303,6 +303,78 @@ qpic_nand: nand-controller@1b30000 { status = "disabled"; }; + pcie_rc: pcie@1c00000 { + compatible = "qcom,pcie-sdx55"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xc8>, + <0x40001000 0x1000>, + <0x40100000 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", + "msi5", "msi6", "msi7", "msi8"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_PIPE_CLK>, + <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep"; + + assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x0200 0x0f>; + iommu-map = <0x0 &apps_smmu 0x0200 0x1>, + <0x100 &apps_smmu 0x0201 0x1>, + <0x200 &apps_smmu 0x0202 0x1>, + <0x300 &apps_smmu 0x0203 0x1>, + <0x400 &apps_smmu 0x0204 0x1>; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_lane>; + phy-names = "pciephy"; + + status = "disabled"; + }; + pcie_ep: pcie-ep@1c00000 { compatible = "qcom,sdx55-pcie-ep"; reg = <0x01c00000 0x3000>,