From patchwork Tue Feb 21 11:55:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 59953 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1824777wrn; Tue, 21 Feb 2023 04:07:37 -0800 (PST) X-Google-Smtp-Source: AK7set93oW0KWX1pjWT8xU6XRdSEOl6QA3znNf/eyoNWWbGywjddfcLTfwRdxUw5JEnQW8DZs/IY X-Received: by 2002:a17:907:7ea0:b0:877:a9d2:e5e9 with SMTP id qb32-20020a1709077ea000b00877a9d2e5e9mr13084661ejc.42.1676981256993; Tue, 21 Feb 2023 04:07:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676981256; cv=none; d=google.com; s=arc-20160816; b=b5iCeNRAAopvN/VDEDW1D6j+DKVLINsGply7yApgwE50RBoyp/X+QIM3sSFJ3Hu7Hb /eUXO5BBM+8Kqep0wdV3VuP3zTU132ytvDAKNl27YhoFAEloL4TCpFVT3OlZoMf2r21V SplJO7LMWOBbjbDAmvZb2TaG7rW3GRkWlbvUmzplRbdJyN59hgMTZZT+QGiQ6Ha5pRFc IpxxZkl/fdqNabtvIt3OvDbZd1huiU5HJIrNPNGSi/89p9J3oQdGOvPlmbLMPUZ9OzDJ 7zc9CWz9bwVY5bJdT2WCU5w2R+PMQNofMoob9uqJ2aRd+gfw9NMV9Z/OqOnZ1MKYnqh3 xWAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6a5pI89qkoqLyXJ9nwUbzxIvoF2RQuyIx3pRsOaEJGo=; b=lvA7FrBj6X0gBnLuUiEJvmRhwSZcU2a5g83u1LNucINNc/gKAvKRedmytce/ka4vlY gtGglVetEti6Nsy2aloO+QyFxqSGkC/1wtxNoOUPmDj+sQPslA30Z0kaKTLDsYKxt40b ch+6TuLfkEJ8EWT2OWwWrzI8GROdtHizXvde61New06RIG3Pf54ucYT/FmcLOHzLGIu6 s2tX73SK8DiUcwDnBhr/mTxmood1W0v0AMQm8ZU9wpoSnHzabTfnkzBiIRXgpsXm8E5K 38VRe4ZWf5LP9f425kdP4/sI3LSTERJG3HPZRn9sdAmmHf4KJl0q64hDuTdPlAcyd/k9 niUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Unbnzsxy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id vl5-20020a17090730c500b008cf5d3457acsi6745716ejb.810.2023.02.21.04.07.12; Tue, 21 Feb 2023 04:07:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Unbnzsxy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234516AbjBUMEI (ORCPT + 99 others); Tue, 21 Feb 2023 07:04:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234422AbjBUMEH (ORCPT ); Tue, 21 Feb 2023 07:04:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 777DD2914A; Tue, 21 Feb 2023 04:03:44 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B5CCA66021E8; Tue, 21 Feb 2023 11:56:54 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676980615; bh=BpYZWFTJBiGmhjWTU8H+MwbDque178dVxUf9q6AYoEg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UnbnzsxyJRtPFFH22SUTAmGrcigk6gs2XYQiArWivPcOCz18uAH49ATux94T3gLxI kyPAT5StglmQQZMAbKMPcl5WHZUptSllxRWl/PKf4vESPlsubjQ89MayEdZJqocmgk i5nycQ7fJLKTKoIlVdN/XrbDWGpH+/HJWrJQSwpb8G4QGFn2l4yrBWoe2P4oaq06RU 1JgLqxt+nSoIJMe54ai22nAY/DrOBCnoMyAOc6sp+psTEiM7tpXiN+91q58XTDbr// IzeJj7UTzdDGRogwrx1/GrIWcwKh4hHf/FVIyyflL0Sg3RkqQ1EUJhRY9K2zPc2xos fEQSMy9IAzY9A== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 46/54] clk: mediatek: Split configuration options for MT8186 clock drivers Date: Tue, 21 Feb 2023 12:55:41 +0100 Message-Id: <20230221115549.360132-47-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> References: <20230221115549.360132-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758442298642859280?= X-GMAIL-MSGID: =?utf-8?q?1758442298642859280?= When building clock drivers for MT8186, some may want to build in only some of them to, for example, get CPUFreq up faster, and some may want to leave out some clock drivers entirely as a machine may not need the Warp Engine or the camera ISP (hence, their clock drivers). Split the various clock drivers in their own configuration options, keeping MT8186 configuration options consistent with other MediaTek SoCs. While at it, also allow building the remaining clock drivers as modules by switching COMMON_CLK_MT8186 to tristate. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/Kconfig | 79 ++++++++++++++++++++++++++++++++++- drivers/clk/mediatek/Makefile | 18 +++++--- 2 files changed, 91 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 0240c1039d64..04b4be419bd0 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -596,7 +596,7 @@ config COMMON_CLK_MT8183_VENCSYS This driver supports MediaTek MT8183 vencsys clocks. config COMMON_CLK_MT8186 - bool "Clock driver for MediaTek MT8186" + tristate "Clock driver for MediaTek MT8186" depends on ARM64 || COMPILE_TEST select COMMON_CLK_MEDIATEK select COMMON_CLK_MEDIATEK_FHCTL @@ -604,6 +604,83 @@ config COMMON_CLK_MT8186 help This driver supports MediaTek MT8186 clocks. +config COMMON_CLK_MT8186_CAMSYS + tristate "Clock driver for MediaTek MT8186 camsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 camsys and camsys_raw clocks. + +config COMMON_CLK_MT8186_IMGSYS + tristate "Clock driver for MediaTek MT8186 imgsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 imgsys and imgsys2 clocks. + +config COMMON_CLK_MT8186_IPESYS + tristate "Clock driver for MediaTek MT8186 ipesys" + depends on COMMON_CLK_MT8186_IMGSYS + default COMMON_CLK_MT8186_IMGSYS + help + This driver supports MediaTek MT8186 ipesys clocks. + +config COMMON_CLK_MT8186_WPESYS + tristate "Clock driver for MediaTek MT8186 wpesys" + depends on COMMON_CLK_MT8186_IMGSYS + default COMMON_CLK_MT8186_IMGSYS + help + This driver supports MediaTek MT8186 Warp Engine clocks. + +config COMMON_CLK_MT8186_IMP_IIC_WRAP + tristate "Clock driver for MediaTek MT8186 imp_iic_wrap" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 imp_iic_wrap clocks. + +config COMMON_CLK_MT8186_MCUSYS + tristate "Clock driver for MediaTek MT8186 mcusys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mcusys clocks. + +config COMMON_CLK_MT8186_MDPSYS + tristate "Clock driver for MediaTek MT8186 mdpsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mdpsys clocks. + +config COMMON_CLK_MT8186_MFGCFG + tristate "Clock driver for MediaTek MT8186 mfgcfg" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mfgcfg clocks. + +config COMMON_CLK_MT8186_MMSYS + tristate "Clock driver for MediaTek MT8186 mmsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 mmsys clocks. + +config COMMON_CLK_MT8186_VDECSYS + tristate "Clock driver for MediaTek MT8186 vdecsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 vdecsys and vdecsys_soc clocks. + +config COMMON_CLK_MT8186_VENCSYS + tristate "Clock driver for MediaTek MT8186 vencsys" + depends on COMMON_CLK_MT8186 + default COMMON_CLK_MT8186 + help + This driver supports MediaTek MT8186 vencsys clocks. + config COMMON_CLK_MT8192 bool "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 63351957f862..6204ad17b7ca 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -87,11 +87,19 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o -obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \ - clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \ - clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \ - clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \ - clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-apmixedsys.o clk-mt8186-infra_ao.o \ + clk-mt8186-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT8186_CAMSYS) += clk-mt8186-cam.o +obj-$(CONFIG_COMMON_CLK_MT8186_IMGSYS) += clk-mt8186-img.o +obj-$(CONFIG_COMMON_CLK_MT8186_IMP_IIC_WRAP) += clk-mt8186-imp_iic_wrap.o +obj-$(CONFIG_COMMON_CLK_MT8186_IPESYS) += clk-mt8186-ipe.o +obj-$(CONFIG_COMMON_CLK_MT8186_MCUSYS) += clk-mt8186-mcu.o +obj-$(CONFIG_COMMON_CLK_MT8186_MDPSYS) += clk-mt8186-mdp.o +obj-$(CONFIG_COMMON_CLK_MT8186_MFGCFG) += clk-mt8186-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8186_MMSYS) += clk-mt8186-mm.o +obj-$(CONFIG_COMMON_CLK_MT8186_VDECSYS) += clk-mt8186-vdec.o +obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o +obj-$(CONFIG_COMMON_CLK_MT8186_WPESYS) += clk-mt8186-wpe.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o