Message ID | 20230221105039.316819-1-robert.marko@sartura.hr |
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[88.207.97.58]) by smtp.googlemail.com with ESMTPSA id bk26-20020a170906b0da00b0089d5aaf85besm6955802ejb.219.2023.02.21.02.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 02:50:42 -0800 (PST) From: Robert Marko <robert.marko@sartura.hr> To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, lars.povlsen@microchip.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, arnd@arndb.de, alexandre.belloni@bootlin.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko <robert.marko@sartura.hr> Subject: [PATCH v2 1/3] arm64: dts: microchip: sparx5: do not use PSCI on reference boards Date: Tue, 21 Feb 2023 11:50:37 +0100 Message-Id: <20230221105039.316819-1-robert.marko@sartura.hr> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758437633175521319?= X-GMAIL-MSGID: =?utf-8?q?1758437633175521319?= |
Series |
[v2,1/3] arm64: dts: microchip: sparx5: do not use PSCI on reference boards
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Commit Message
Robert Marko
Feb. 21, 2023, 10:50 a.m. UTC
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that
is shipped does not implement it as well.
I have tried flashing the latest BSP 2022.12 U-boot which did not work.
After contacting Microchip, they confirmed that there is no ATF for the
SoC nor PSCI implementation which is unfortunate in 2023.
So, disable PSCI as otherwise kernel crashes as soon as it tries probing
PSCI with, and the crash is only visible if earlycon is used.
Since PSCI is not implemented, switch core bringup to use spin-tables
which are implemented in the vendor U-boot and actually work.
Tested on PCB134 with eMMC (VSC5640EV).
Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
Changes in v2:
* As suggested by Arnd, disable PSCI only on reference boards
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +-
arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 12 ++++++++++++
2 files changed, 13 insertions(+), 1 deletion(-)
Comments
Hi Robert, I find this very useful since the Sparx5 SoC does not support TFA and therefore cannot provide PSCI on its own, as you also state below. Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com> On Tue, 2023-02-21 at 11:50 +0100, Robert Marko wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that > is shipped does not implement it as well. > > I have tried flashing the latest BSP 2022.12 U-boot which did not work. > After contacting Microchip, they confirmed that there is no ATF for the > SoC nor PSCI implementation which is unfortunate in 2023. > > So, disable PSCI as otherwise kernel crashes as soon as it tries probing > PSCI with, and the crash is only visible if earlycon is used. > > Since PSCI is not implemented, switch core bringup to use spin-tables > which are implemented in the vendor U-boot and actually work. > > Tested on PCB134 with eMMC (VSC5640EV). > > Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > --- > Changes in v2: > * As suggested by Arnd, disable PSCI only on reference boards > --- > arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +- > arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 12 ++++++++++++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi > b/arch/arm64/boot/dts/microchip/sparx5.dtsi > index 0367a00a269b3..5eae6e7fd248e 100644 > --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi > +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi > @@ -61,7 +61,7 @@ arm-pmu { > interrupt-affinity = <&cpu0>, <&cpu1>; > }; > > - psci { > + psci: psci { > compatible = "arm,psci-0.2"; > method = "smc"; > }; > diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > index 9d1a082de3e29..32bb76b3202a0 100644 > --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi > @@ -6,6 +6,18 @@ > /dts-v1/; > #include "sparx5.dtsi" > > +&psci { > + status = "disabled"; > +}; > + > +&cpu0 { > + enable-method = "spin-table"; > +}; > + > +&cpu1 { > + enable-method = "spin-table"; > +}; > + > &uart0 { > status = "okay"; > }; > -- > 2.39.2 > BR Steen
On 21/02/2023 11:50, Robert Marko wrote: > PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that > is shipped does not implement it as well. > > I have tried flashing the latest BSP 2022.12 U-boot which did not work. > After contacting Microchip, they confirmed that there is no ATF for the > SoC nor PSCI implementation which is unfortunate in 2023. > > So, disable PSCI as otherwise kernel crashes as soon as it tries probing > PSCI with, and the crash is only visible if earlycon is used. > > Since PSCI is not implemented, switch core bringup to use spin-tables > which are implemented in the vendor U-boot and actually work. > > Tested on PCB134 with eMMC (VSC5640EV). > > Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > --- > Changes in v2: > * As suggested by Arnd, disable PSCI only on reference boards Patch seemed forgotten, so I applied it. https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git/log/?h=next/dt64 Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b3..5eae6e7fd248e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -61,7 +61,7 @@ arm-pmu { interrupt-affinity = <&cpu0>, <&cpu1>; }; - psci { + psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 9d1a082de3e29..32bb76b3202a0 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -6,6 +6,18 @@ /dts-v1/; #include "sparx5.dtsi" +&psci { + status = "disabled"; +}; + +&cpu0 { + enable-method = "spin-table"; +}; + +&cpu1 { + enable-method = "spin-table"; +}; + &uart0 { status = "okay"; };