From patchwork Mon Feb 20 15:01:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 59519 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp1355471wrn; Mon, 20 Feb 2023 07:05:54 -0800 (PST) X-Google-Smtp-Source: AK7set+IrS7WFbf+A7d3MRIEDqh7fzYxcQODk0lkKQtn4YFJ7577A/+J7s7k7U+mNsrH1eoEesnw X-Received: by 2002:a17:902:fac5:b0:19a:85d9:93fd with SMTP id ld5-20020a170902fac500b0019a85d993fdmr1429423plb.22.1676905554237; Mon, 20 Feb 2023 07:05:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676905554; cv=none; d=google.com; s=arc-20160816; b=fV4A1fkhH6zOYdr/Z9HTKGzoM62HQTVCo2xqtg2ugMgbFgj9qoIeHRslmuWLP6Q7z9 CV90DmVxs+KgkwI0NnK6IjsjcqABR9Irs6HVDdUrO/xGOstsoTkkZplT4RV8jqHZ7d4y EtdhAnljqsyYpGaNP2Td15rEHYX4Vs10qffoUeV/T/An1ZwdC15wVUQxUipdKNN0Ji5x XHetSZN7q8yU7eMgeP7h6+D57Sz96CO1iC9ElL8I98zewJomdQ3Inmuj/DxGlmAqCshh 2cWKCJy+8ecIMh29tcF4/rLoQ1A5m/UTmDojOKgKGyJayO0CZRNXtrTY9IlllMGfn1e7 ZTNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tTk4OY4LfNzpvYIsx2e012BzuyNxcliGVnaJL0P84So=; b=tiG1DzFi1lkW8uXdpNFEEm0+asLHiXcFVTodRQGFkv5OiUwe+PI6f1dv6wQ2tplaiU qJRepPgzIfcGe1fV3JpZ0MTzFkJ74eO/SIeDwlXehIOPergEVQDBDxpsmBaZUw3Mx1pX 4hpbHW9b0wK4rMwxA9K16Fc9UTFNCPxNGNm0Iir99uNfnurT2nZ65e80qYmvujGx2FOF eVjaCc1f/Q6sHTOy95h3dWfuWpexnbWtLsr3ybT/XqjZQFoXPNo4uI8yVTuMPCL+jdnp fh82tuGc68pDhS8JQejeilEm1OsgM0UcWJy3LKBhX/MgHT7qkwSCcMswC+O9s16kNGUF X0Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=feWv+Gbd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q16-20020a170902dad000b0019ad76073a2si1366336plx.419.2023.02.20.07.05.41; Mon, 20 Feb 2023 07:05:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=feWv+Gbd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232854AbjBTPFB (ORCPT + 99 others); Mon, 20 Feb 2023 10:05:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232314AbjBTPEh (ORCPT ); Mon, 20 Feb 2023 10:04:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CA6364492; Mon, 20 Feb 2023 07:02:49 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B25F966021CC; Mon, 20 Feb 2023 15:02:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1676905347; bh=qI37eAVXpXgAjG1sJQwIW4vaDPf2H9q2nvTIZKlPjrA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=feWv+GbdqoXRxlb40FKN7ey+pcKIxAunXKLRx9IOt3hGxo7wdTNXr0t5h/HkgDYQD eQReTEmpRpNPA1b3yYYkLa3B1nRVg16Xm+LHk2EgMXlPTc2xtaVA9F1ADA9N7Mpby2 HggVB6+gM2D8GKtBqBUXORFxUCgkytaZsqf1O9BbXe8Ts6DKZgpQBuK8uRwsesvk6D HGCVThfIFx84aCOZqJ+0fDZIutyaBogpxVVX5GUxUKfLPncRM7ENOARytYc9ndT7Bg i8PbOcz7EJnTwGFqsWY3EaBF52LojzUNQMTjMAmTfupxkaRwU9ojYqQh1uPD0FR5Vz Ea8TXgXsrIUpQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 51/55] clk: mediatek: mt8135: Properly use CLK_IS_CRITICAL flag Date: Mon, 20 Feb 2023 16:01:07 +0100 Message-Id: <20230220150111.77897-52-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> References: <20230220150111.77897-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758362918542885475?= X-GMAIL-MSGID: =?utf-8?q?1758362918542885475?= Instead of calling clk_prepare_enable() for clocks that shall stay enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that. Fixes: a8aede794843 ("clk: mediatek: Add basic clocks for Mediatek MT8135.") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai --- drivers/clk/mediatek/clk-mt8135.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 2a9405b552c6..1c76c0003f99 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -2,6 +2,8 @@ /* * Copyright (c) 2014 MediaTek Inc. * Author: James Liao + * Copyright (c) 2023 Collabora, Ltd. + * AngeloGioacchino Del Regno */ #include @@ -390,7 +392,7 @@ static const struct mtk_composite top_muxes[] __initconst = { MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31), /* CLK_CFG_9 */ MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7), - MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15), + MUX_GATE_FLAGS(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15, CLK_IS_CRITICAL), MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23), MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31), }; @@ -404,6 +406,10 @@ static const struct mtk_gate_regs infra_cg_regs = { #define GATE_ICG(_id, _name, _parent, _shift) \ GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) +#define GATE_ICG_AO(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &infra_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IS_CRITICAL) + static const struct mtk_gate infra_clks[] __initconst = { GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23), GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22), @@ -411,7 +417,7 @@ static const struct mtk_gate infra_clks[] __initconst = { GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20), GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16), GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15), - GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), + GATE_ICG_AO(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8), GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7), GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6), GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5), @@ -534,8 +540,6 @@ static void __init mtk_topckgen_init(struct device_node *node) ARRAY_SIZE(top_muxes), base, &mt8135_clk_lock, clk_data); - clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", @@ -553,8 +557,6 @@ static void __init mtk_infrasys_init(struct device_node *node) mtk_clk_register_gates(NULL, node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); - clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n",