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Date: Sun, 19 Feb 2023 01:28:28 -0800
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Subject: [PATCH v1 31/51] perf vendor events intel: Refresh westmereep-dp
events
From: Ian Rogers <irogers@google.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Zhengjun Xing <zhengjun.xing@linux.intel.com>,
Sandipan Das <sandipan.das@amd.com>,
James Clark <james.clark@arm.com>,
Kajol Jain <kjain@linux.ibm.com>,
John Garry <john.g.garry@oracle.com>,
Kan Liang <kan.liang@linux.intel.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Andrii Nakryiko <andrii@kernel.org>,
Eduard Zingerman <eddyz87@gmail.com>,
Suzuki Poulouse <suzuki.poulose@arm.com>,
Leo Yan <leo.yan@linaro.org>,
Florian Fischer <florian.fischer@muhq.space>,
Ravi Bangoria <ravi.bangoria@amd.com>,
Jing Zhang <renyu.zj@linux.alibaba.com>,
Sean Christopherson <seanjc@google.com>,
Athira Rajeev <atrajeev@linux.vnet.ibm.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
Perry Taylor <perry.taylor@intel.com>,
Caleb Biggers <caleb.biggers@intel.com>
Cc: Stephane Eranian <eranian@google.com>,
Ian Rogers <irogers@google.com>
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|
| Series |
shadow metric clean up and improvements
|
|
Commit Message
Ian Rogers
Feb. 19, 2023, 9:28 a.m. UTC
Update the westmereep-dp events from 3 to 4. Generation was done
using https://github.com/intel/perfmon.
The most notable change is in corrections to event descriptions.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json | 2 +-
.../perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index bc2c4e756f44..1c6eef118e61 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -28,7 +28,7 @@ GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v54,skylake,core GenuineIntel-6-55-[01234],v1.29,skylakex,core GenuineIntel-6-86,v1.20,snowridgex,core GenuineIntel-6-8[CD],v1.10,tigerlake,core -GenuineIntel-6-2C,v3,westmereep-dp,core +GenuineIntel-6-2C,v4,westmereep-dp,core GenuineIntel-6-25,v3,westmereep-sp,core GenuineIntel-6-2F,v3,westmereex,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json index 5c897da3cd6b..4dae735fb636 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -182,7 +182,7 @@ "UMask": "0x20" }, { - "BriefDescription": "L2 lines alloacated", + "BriefDescription": "L2 lines allocated", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index ef635bff1522..f75084309041 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -56,7 +56,7 @@ "UMask": "0x80" }, { - "BriefDescription": "DTLB misses casued by low part of address", + "BriefDescription": "DTLB misses caused by low part of address", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000",