From patchwork Sat Feb 18 21:13:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgecombe, Rick P" X-Patchwork-Id: 58987 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp554307wrn; Sat, 18 Feb 2023 13:18:09 -0800 (PST) X-Google-Smtp-Source: AK7set+creX6ToG1m6iQfy7mHlo9aVnFumkE540m61EWX3V7Bdr1CB8tx4Fd1NQwVoOm4yNU86WQ X-Received: by 2002:a17:902:d4cd:b0:19a:831d:1ef with SMTP id o13-20020a170902d4cd00b0019a831d01efmr1888502plg.69.1676755089388; Sat, 18 Feb 2023 13:18:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1676755089; cv=none; d=google.com; s=arc-20160816; b=TTC3A56zyYB09QXpa6ejdXbS4YL10kUCTbmJPTzLEJ13jHI3KnewUmuf1ll3tmmdJd f8/nDhC3VsGLgLyULQwTM3fgMMqlG7jPlDzw8nz2knIj/KJZAn/hZaGsPfWSOMWx5IfL KMpf+E0/Jjus6LUkYTgitC9AlGb3fPDBH+jQ0+WxeH8CXY13m/nOXNTpQzw6LTDIXCV4 cu/Zizbs2lsFiRq4NI3qnqMUIY6HslkMnlMiie4Yy/lfcR8s6rfZdqudliEMY4SaHbJU hmBC0BsxnU/RbgHIWVItEiHCR2axJzLhihD1i/f0a/NRPv7UiP34/DNcexf3xO+MPMyG jLFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=1qF79w3tBeVewLR/G4DWxS5EV45VnTvhj/Fuk26jDzE=; b=fqFivyw90XbaBDShkXuyOamIHdF0mn1lF7aHm3v+M0v3TPfMACUxVrWVWHpG21WmRY XGEpLIyvrsodZLQIMFothMSAAZdPmoDGa8Z1H+CtSMtUuCI0lybeSE7zrabqPpWU6AoJ C90SHqzJ6WQF5zBLmXU8OnL/0jUSbGvEpfX9BQ5fya4nbGq1bIuyOX0VOlQkgO7Q4DCD B7NQsvYWnmpmxk98T+FTpYdZQCu0E8JyqP3OPpudyBlJ/ZYzxDB1WEZ/uC/nio6O8pNv r29ng+VynyQ2eAZtbs2Pcimc4RqpVkbOGsd2F7I8wroBoKb6C62GN/FPM2smAr3qsD3T 8TOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="jIjo+/B9"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x6-20020a170902b40600b0019a7ef5e99fsi3664447plr.86.2023.02.18.13.17.57; Sat, 18 Feb 2023 13:18:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="jIjo+/B9"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229925AbjBRVRU (ORCPT + 99 others); Sat, 18 Feb 2023 16:17:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229917AbjBRVQO (ORCPT ); Sat, 18 Feb 2023 16:16:14 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CB7317153; Sat, 18 Feb 2023 13:16:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676754964; x=1708290964; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=7jVlFLlhK4ICVGezzTiai5C8Zlo8EPl2MrkiyOokM44=; b=jIjo+/B93XicTCsEZ6YI7wCaM17bmUqn+8b3kYCji4Uk/es7ueHsMb2a 0CsS3iXfG20j5cLvSUq3c5IkVdo5dL0/IlP6/X085mZbyR2T2wEdmpPWe L/C7k8ZXInj7flNpTjSBnOXRYQVf335k9McQ/CiJqqSfnDkcQIb+jaZDa ITR3tznashrayZRxVvm1TjwIhJNRr6P2qDtYE4dgQHYtAEgPeHH68LRhQ eCEDP79q6BYKdwIYANNr77dxScP94HpoSXcHCgJuNPUHgI3KXMQ+FIp8o pF+NT2KSKcbM75eCkPD/YqSZDSx4MGz+6BaT8+duoVZzbF1RN4bs3JzKO g==; X-IronPort-AV: E=McAfee;i="6500,9779,10625"; a="418427203" X-IronPort-AV: E=Sophos;i="5.97,309,1669104000"; d="scan'208";a="418427203" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2023 13:16:01 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10625"; a="664241594" X-IronPort-AV: E=Sophos;i="5.97,309,1669104000"; d="scan'208";a="664241594" Received: from adityava-mobl1.amr.corp.intel.com (HELO rpedgeco-desk.amr.corp.intel.com) ([10.209.80.223]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Feb 2023 13:16:00 -0800 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org, Andrew.Cooper3@citrix.com, christina.schimpe@intel.com, david@redhat.com, debug@rivosinc.com Cc: rick.p.edgecombe@intel.com Subject: [PATCH v6 06/41] x86/fpu: Add helper for modifying xstate Date: Sat, 18 Feb 2023 13:13:58 -0800 Message-Id: <20230218211433.26859-7-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230218211433.26859-1-rick.p.edgecombe@intel.com> References: <20230218211433.26859-1-rick.p.edgecombe@intel.com> X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1758205144192621920?= X-GMAIL-MSGID: =?utf-8?q?1758205144192621920?= Just like user xfeatures, supervisor xfeatures can be active in the registers or present in the task FPU buffer. If the registers are active, the registers can be modified directly. If the registers are not active, the modification must be performed on the task FPU buffer. When the state is not active, the kernel could perform modifications directly to the buffer. But in order for it to do that, it needs to know where in the buffer the specific state it wants to modify is located. Doing this is not robust against optimizations that compact the FPU buffer, as each access would require computing where in the buffer it is. The easiest way to modify supervisor xfeature data is to force restore the registers and write directly to the MSRs. Often times this is just fine anyway as the registers need to be restored before returning to userspace. Do this for now, leaving buffer writing optimizations for the future. Add a new function fpregs_lock_and_load() that can simultaneously call fpregs_lock() and do this restore. Also perform some extra sanity checks in this function since this will be used in non-fpu focused code. Tested-by: Pengfei Xu Tested-by: John Allen Reviewed-by: Kees Cook Suggested-by: Thomas Gleixner Signed-off-by: Rick Edgecombe --- v6: - Drop "but appear to work" (Boris) v5: - Fix spelling error (Boris) - Don't export fpregs_lock_and_load() (Boris) v3: - Rename to fpregs_lock_and_load() to match the unlocking fpregs_unlock(). (Kees) - Elaborate in comment about helper. (Dave) v2: - Drop optimization of writing directly the buffer, and change API accordingly. - fpregs_lock_and_load() suggested by tglx - Some commit log verbiage from dhansen --- arch/x86/include/asm/fpu/api.h | 9 +++++++++ arch/x86/kernel/fpu/core.c | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/x86/include/asm/fpu/api.h b/arch/x86/include/asm/fpu/api.h index 503a577814b2..aadc6893dcaa 100644 --- a/arch/x86/include/asm/fpu/api.h +++ b/arch/x86/include/asm/fpu/api.h @@ -82,6 +82,15 @@ static inline void fpregs_unlock(void) preempt_enable(); } +/* + * FPU state gets lazily restored before returning to userspace. So when in the + * kernel, the valid FPU state may be kept in the buffer. This function will force + * restore all the fpu state to the registers early if needed, and lock them from + * being automatically saved/restored. Then FPU state can be modified safely in the + * registers, before unlocking with fpregs_unlock(). + */ +void fpregs_lock_and_load(void); + #ifdef CONFIG_X86_DEBUG_FPU extern void fpregs_assert_state_consistent(void); #else diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c index caf33486dc5e..f851558b673f 100644 --- a/arch/x86/kernel/fpu/core.c +++ b/arch/x86/kernel/fpu/core.c @@ -753,6 +753,24 @@ void switch_fpu_return(void) } EXPORT_SYMBOL_GPL(switch_fpu_return); +void fpregs_lock_and_load(void) +{ + /* + * fpregs_lock() only disables preemption (mostly). So modifying state + * in an interrupt could screw up some in progress fpregs operation. + * Warn about it. + */ + WARN_ON_ONCE(!irq_fpu_usable()); + WARN_ON_ONCE(current->flags & PF_KTHREAD); + + fpregs_lock(); + + fpregs_assert_state_consistent(); + + if (test_thread_flag(TIF_NEED_FPU_LOAD)) + fpregs_restore_userregs(); +} + #ifdef CONFIG_X86_DEBUG_FPU /* * If current FPU state according to its tracking (loaded FPU context on this