[v12,04/10] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver
Commit Message
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Add the bindings for the CPR3 driver to the documentation.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
[Konrad: Make binding check pass; update AGdR's email]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/soc/qcom/qcom,cpr3.yaml | 289 +++++++++++++++++++++
1 file changed, 289 insertions(+)
Comments
On Wed, 28 Jun 2023 16:00:43 +0200, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>
> Add the bindings for the CPR3 driver to the documentation.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> [Konrad: Make binding check pass; update AGdR's email]
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../devicetree/bindings/soc/qcom/qcom,cpr3.yaml | 289 +++++++++++++++++++++
> 1 file changed, 289 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/iio/adc/ti,palmas-gpadc.example.dtb: /example-0/pmic: failed to match any schema with compatible: ['ti,twl6035-pmic', 'ti,palmas-pmic']
Documentation/devicetree/bindings/iio/adc/ti,palmas-gpadc.example.dtb: /example-0/pmic: failed to match any schema with compatible: ['ti,twl6035-pmic', 'ti,palmas-pmic']
Documentation/devicetree/bindings/i2c/qcom,i2c-cci.example.dtb: /example-0/cci@ac4a000/i2c-bus@1/camera@60: failed to match any schema with compatible: ['ovti,ov7251']
Documentation/devicetree/bindings/net/marvell,mvusb.example.dtb: /example-0/usb/mdio@1/switch@0: failed to match any schema with compatible: ['marvell,mv88e6190']
Documentation/devicetree/bindings/net/qca,ar71xx.example.dtb: /example-0/ethernet@1a000000/mdio/switch@10: failed to match any schema with compatible: ['qca,ar9331-switch']
Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.example.dtb: /example-0/memory-controller@13410000/ethernet@6: failed to match any schema with compatible: ['davicom,dm9000']
Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.example.dtb: /example-0/iomcu@ffd7e000: failed to match any schema with compatible: ['hisilicon,hi3660-iomcu', 'syscon']
Documentation/devicetree/bindings/leds/common.example.dtb: /example-2/i2c/led-controller@30: failed to match any schema with compatible: ['panasonic,an30259a']
Documentation/devicetree/bindings/dma/dma-router.example.dtb: /example-0/dma-router@4a002b78: failed to match any schema with compatible: ['ti,dra7-dma-crossbar']
Documentation/devicetree/bindings/dma/dma-controller.example.dtb: /example-0/dma-controller@48000000: failed to match any schema with compatible: ['ti,omap-sdma']
Documentation/devicetree/bindings/media/rockchip-isp1.example.dtb: /example-0/parent/i2c/camera@36: failed to match any schema with compatible: ['ovti,ov5695']
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.example.dtb: /example-1/syscon@20e00000: failed to match any schema with compatible: ['sprd,sc9863a-glbregs', 'syscon', 'simple-mfd']
Documentation/devicetree/bindings/clock/milbeaut-clock.example.dtb: /example-2/serial@1e700010: failed to match any schema with compatible: ['socionext,milbeaut-usio-uart']
Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.example.dtb: /example-0/cpuctrl@a22000/clock@0: failed to match any schema with compatible: ['hisilicon,hix5hd2-clock']
Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.example.dtb: /example-0/peripheral-controller@8a20000/phy@850: failed to match any schema with compatible: ['hisilicon,hi3798cv200-combphy']
Documentation/devicetree/bindings/arm/hisilicon/controller/sysctrl.example.dtb: /example-0/system-controller@802000/clock@0: failed to match any schema with compatible: ['hisilicon,hi3620-clock']
Documentation/devicetree/bindings/sound/audio-graph-card2.example.dtb: /example-0/cpu: failed to match any schema with compatible: ['cpu-driver']
Documentation/devicetree/bindings/sound/audio-graph-card2.example.dtb: /example-0/codec: failed to match any schema with compatible: ['codec-driver']
Documentation/devicetree/bindings/input/sprd,sc27xx-vibrator.example.dtb: /example-0/pmic@0: failed to match any schema with compatible: ['sprd,sc2731']
Documentation/devicetree/bindings/input/mediatek,pmic-keys.example.dtb: /example-0/pmic: failed to match any schema with compatible: ['mediatek,mt6397']
Documentation/devicetree/bindings/thermal/brcm,avs-ro-thermal.example.dtb: /example-0/avs-monitor@7d5d2000: failed to match any schema with compatible: ['brcm,bcm2711-avs-monitor', 'syscon', 'simple-mfd']
Documentation/devicetree/bindings/thermal/imx-thermal.example.dtb: /example-0/anatop@20c8000: failed to match any schema with compatible: ['fsl,imx6q-anatop', 'syscon', 'simple-mfd']
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-1: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-2: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-3: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230217-topic-cpr3h-v12-4-1a4d050e1e67@linaro.org
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Wed, Jun 28, 2023 at 04:00:43PM +0200, Konrad Dybcio wrote:
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>
> Add the bindings for the CPR3 driver to the documentation.
Bindings are for h/w, not drivers.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> [Konrad: Make binding check pass; update AGdR's email]
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> .../devicetree/bindings/soc/qcom/qcom,cpr3.yaml | 289 +++++++++++++++++++++
> 1 file changed, 289 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
> new file mode 100644
> index 000000000000..46b94dffaf85
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
> @@ -0,0 +1,289 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
Drop quotes
> +
> +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
> +
> +description:
> + CPR (Core Power Reduction) is a technology to reduce core power of a CPU
> + (or another device). Each OPP of a device corresponds to a "corner" that
> + has a range of valid voltages for a particular frequency.
> + The CPR monitors dynamic factors such as temperature, etc. and suggests
> + or (in the CPR-hardened case) applies voltage adjustments to save power
> + and meet silicon characteristic requirements for a given chip unit.
> +
> +maintainers:
> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - description: CPRv3 controller
> + items:
> + - const: qcom,cpr3
> + - description: CPRv4 controller
> + items:
> + - const: qcom,cpr4
> + - description: CPRv4-Hardened controller
> + items:
> + - enum:
> + - qcom,msm8998-cprh
> + - qcom,sdm630-cprh
> + - const: qcom,cprh
> +
> + reg:
> + description: Base address and size of the CPR controller(s)
> + maxItems: 2
What is each entry?
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: CPR reference clock
> +
> + vdd-supply:
> + description: Autonomous Phase Control (APC) or other power supply
> +
> + '#power-domain-cells':
> + const: 1
> +
> + qcom,acc:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: phandle to syscon for writing ACC settings
> +
> + nvmem-cells:
> + description: Cells containing the fuse corners and revision data
> + maxItems: 32
> +
> + nvmem-cell-names:
> + maxItems: 32
> +
> + operating-points-v2: true
> +
> + power-domains: true
Need to define how many.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - operating-points-v2
> + - "#power-domain-cells"
> + - nvmem-cells
> + - nvmem-cell-names
> +
> +additionalProperties: false
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,msm8998-cprh
> + then:
> + properties:
> + nvmem-cell-names:
> + items:
> + - const: cpr_speed_bin
> + - const: cpr_fuse_revision
> + - const: cpr0_quotient1
> + - const: cpr0_quotient2
> + - const: cpr0_quotient3
> + - const: cpr0_quotient4
> + - const: cpr0_quotient_offset2
> + - const: cpr0_quotient_offset3
> + - const: cpr0_quotient_offset4
> + - const: cpr0_init_voltage1
> + - const: cpr0_init_voltage2
> + - const: cpr0_init_voltage3
> + - const: cpr0_init_voltage4
> + - const: cpr0_ring_osc1
> + - const: cpr0_ring_osc2
> + - const: cpr0_ring_osc3
> + - const: cpr0_ring_osc4
> + - const: cpr1_quotient1
> + - const: cpr1_quotient2
> + - const: cpr1_quotient3
> + - const: cpr1_quotient4
> + - const: cpr1_quotient_offset2
> + - const: cpr1_quotient_offset3
> + - const: cpr1_quotient_offset4
> + - const: cpr1_init_voltage1
> + - const: cpr1_init_voltage2
> + - const: cpr1_init_voltage3
> + - const: cpr1_init_voltage4
> + - const: cpr1_ring_osc1
> + - const: cpr1_ring_osc2
> + - const: cpr1_ring_osc3
> + - const: cpr1_ring_osc4
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-msm8998.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "qcom,kryo280";
> + device_type = "cpu";
> + reg = <0x0 0x0>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + power-domains = <&apc_cprh 0>;
> + power-domain-names = "cprh";
The name should be local to the device, not based on the provider.
Do you really need a name here with only 1?
> + };
> +
> + cpu@100 {
> + compatible = "qcom,kryo280";
> + device_type = "cpu";
> + reg = <0x0 0x100>;
> + operating-points-v2 = <&cpu4_opp_table>;
> + power-domains = <&apc_cprh 1>;
> + power-domain-names = "cprh";
> + };
> + };
> +
> + cpu0_opp_table: opp-table-cpu0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-1843200000 {
> + opp-hz = /bits/ 64 <1843200000>;
> + required-opps = <&cprh_opp3>;
> + };
> +
> + opp-1094400000 {
> + opp-hz = /bits/ 64 <1094400000>;
> + required-opps = <&cprh_opp2>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&cprh_opp1>;
> + };
> + };
> +
> + cpu4_opp_table: opp-table-cpu4 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-2208000000 {
> + opp-hz = /bits/ 64 <2208000000>;
> + required-opps = <&cprh_opp3>;
> + };
> +
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + required-opps = <&cprh_opp2>;
> + };
> +
> + opp-300000000 {
> + opp-hz = /bits/ 64 <300000000>;
> + required-opps = <&cprh_opp1>;
> + };
> + };
> +
> + cprh_opp_table: opp-table-cprh {
> + compatible = "operating-points-v2-qcom-level";
> +
> + cprh_opp1: opp-1 {
> + opp-level = <1>;
> + qcom,opp-fuse-level = <1>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp2: opp-2 {
> + opp-level = <2>;
> + qcom,opp-fuse-level = <2>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> +
> + cprh_opp3: opp-3 {
> + opp-level = <3>;
> + qcom,opp-fuse-level = <2 3>;
> + qcom,opp-cloop-vadj = <0>;
> + qcom,opp-oloop-vadj = <0>;
> + };
> + };
> +
> + apc_cprh: power-controller@179c8000 {
> + compatible = "qcom,msm8998-cprh", "qcom,cprh";
> + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
> + clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
> +
> + operating-points-v2 = <&cprh_opp_table>;
> + #power-domain-cells = <1>;
> +
> + nvmem-cells = <&cpr_efuse_speedbin>,
> + <&cpr_fuse_revision>,
> + <&cpr_quot0_pwrcl>,
> + <&cpr_quot1_pwrcl>,
> + <&cpr_quot2_pwrcl>,
> + <&cpr_quot3_pwrcl>,
> + <&cpr_quot_offset1_pwrcl>,
> + <&cpr_quot_offset2_pwrcl>,
> + <&cpr_quot_offset3_pwrcl>,
> + <&cpr_init_voltage0_pwrcl>,
> + <&cpr_init_voltage1_pwrcl>,
> + <&cpr_init_voltage2_pwrcl>,
> + <&cpr_init_voltage3_pwrcl>,
> + <&cpr_ro_sel0_pwrcl>,
> + <&cpr_ro_sel1_pwrcl>,
> + <&cpr_ro_sel2_pwrcl>,
> + <&cpr_ro_sel3_pwrcl>,
> + <&cpr_quot0_perfcl>,
> + <&cpr_quot1_perfcl>,
> + <&cpr_quot2_perfcl>,
> + <&cpr_quot3_perfcl>,
> + <&cpr_quot_offset1_perfcl>,
> + <&cpr_quot_offset2_perfcl>,
> + <&cpr_quot_offset3_perfcl>,
> + <&cpr_init_voltage0_perfcl>,
> + <&cpr_init_voltage1_perfcl>,
> + <&cpr_init_voltage2_perfcl>,
> + <&cpr_init_voltage3_perfcl>,
> + <&cpr_ro_sel0_perfcl>,
> + <&cpr_ro_sel1_perfcl>,
> + <&cpr_ro_sel2_perfcl>,
> + <&cpr_ro_sel3_perfcl>;
> + nvmem-cell-names = "cpr_speed_bin",
> + "cpr_fuse_revision",
> + "cpr0_quotient1",
> + "cpr0_quotient2",
> + "cpr0_quotient3",
> + "cpr0_quotient4",
> + "cpr0_quotient_offset2",
> + "cpr0_quotient_offset3",
> + "cpr0_quotient_offset4",
> + "cpr0_init_voltage1",
> + "cpr0_init_voltage2",
> + "cpr0_init_voltage3",
> + "cpr0_init_voltage4",
> + "cpr0_ring_osc1",
> + "cpr0_ring_osc2",
> + "cpr0_ring_osc3",
> + "cpr0_ring_osc4",
> + "cpr1_quotient1",
> + "cpr1_quotient2",
> + "cpr1_quotient3",
> + "cpr1_quotient4",
> + "cpr1_quotient_offset2",
> + "cpr1_quotient_offset3",
> + "cpr1_quotient_offset4",
> + "cpr1_init_voltage1",
> + "cpr1_init_voltage2",
> + "cpr1_init_voltage3",
> + "cpr1_init_voltage4",
> + "cpr1_ring_osc1",
> + "cpr1_ring_osc2",
> + "cpr1_ring_osc3",
> + "cpr1_ring_osc4";
> + };
> +...
>
> --
> 2.41.0
>
On 28.06.2023 18:03, Rob Herring wrote:
> On Wed, Jun 28, 2023 at 04:00:43PM +0200, Konrad Dybcio wrote:
>> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>>
>> Add the bindings for the CPR3 driver to the documentation.
>
> Bindings are for h/w, not drivers.
This shows how ancient this patch is, from before it was
common knowledge ;)
>
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
>> [Konrad: Make binding check pass; update AGdR's email]
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>> .../devicetree/bindings/soc/qcom/qcom,cpr3.yaml | 289 +++++++++++++++++++++
>> 1 file changed, 289 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>> new file mode 100644
>> index 000000000000..46b94dffaf85
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml
>> @@ -0,0 +1,289 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
> Drop quotes
Ack
>
>> +
>> +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
>> +
>> +description:
>> + CPR (Core Power Reduction) is a technology to reduce core power of a CPU
>> + (or another device). Each OPP of a device corresponds to a "corner" that
>> + has a range of valid voltages for a particular frequency.
>> + The CPR monitors dynamic factors such as temperature, etc. and suggests
>> + or (in the CPR-hardened case) applies voltage adjustments to save power
>> + and meet silicon characteristic requirements for a given chip unit.
>> +
>> +maintainers:
>> + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - description: CPRv3 controller
>> + items:
>> + - const: qcom,cpr3
>> + - description: CPRv4 controller
>> + items:
>> + - const: qcom,cpr4
>> + - description: CPRv4-Hardened controller
>> + items:
>> + - enum:
>> + - qcom,msm8998-cprh
>> + - qcom,sdm630-cprh
>> + - const: qcom,cprh
>> +
>> + reg:
>> + description: Base address and size of the CPR controller(s)
>> + maxItems: 2
>
> What is each entry?
I thought the description was clear enough, but I'll add items:.
>
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: CPR reference clock
>> +
>> + vdd-supply:
>> + description: Autonomous Phase Control (APC) or other power supply
>> +
>> + '#power-domain-cells':
>> + const: 1
>> +
>> + qcom,acc:
>> + $ref: /schemas/types.yaml#/definitions/phandle
>> + description: phandle to syscon for writing ACC settings
>> +
>> + nvmem-cells:
>> + description: Cells containing the fuse corners and revision data
>> + maxItems: 32
>> +
>> + nvmem-cell-names:
>> + maxItems: 32
>> +
>> + operating-points-v2: true
>> +
>> + power-domains: true
>
> Need to define how many.
Ack
>
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - operating-points-v2
>> + - "#power-domain-cells"
>> + - nvmem-cells
>> + - nvmem-cell-names
>> +
>> +additionalProperties: false
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - qcom,msm8998-cprh
>> + then:
>> + properties:
>> + nvmem-cell-names:
>> + items:
>> + - const: cpr_speed_bin
>> + - const: cpr_fuse_revision
>> + - const: cpr0_quotient1
>> + - const: cpr0_quotient2
>> + - const: cpr0_quotient3
>> + - const: cpr0_quotient4
>> + - const: cpr0_quotient_offset2
>> + - const: cpr0_quotient_offset3
>> + - const: cpr0_quotient_offset4
>> + - const: cpr0_init_voltage1
>> + - const: cpr0_init_voltage2
>> + - const: cpr0_init_voltage3
>> + - const: cpr0_init_voltage4
>> + - const: cpr0_ring_osc1
>> + - const: cpr0_ring_osc2
>> + - const: cpr0_ring_osc3
>> + - const: cpr0_ring_osc4
>> + - const: cpr1_quotient1
>> + - const: cpr1_quotient2
>> + - const: cpr1_quotient3
>> + - const: cpr1_quotient4
>> + - const: cpr1_quotient_offset2
>> + - const: cpr1_quotient_offset3
>> + - const: cpr1_quotient_offset4
>> + - const: cpr1_init_voltage1
>> + - const: cpr1_init_voltage2
>> + - const: cpr1_init_voltage3
>> + - const: cpr1_init_voltage4
>> + - const: cpr1_ring_osc1
>> + - const: cpr1_ring_osc2
>> + - const: cpr1_ring_osc3
>> + - const: cpr1_ring_osc4
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,gcc-msm8998.h>
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "qcom,kryo280";
>> + device_type = "cpu";
>> + reg = <0x0 0x0>;
>> + operating-points-v2 = <&cpu0_opp_table>;
>> + power-domains = <&apc_cprh 0>;
>> + power-domain-names = "cprh";
>
> The name should be local to the device, not based on the provider.
>
> Do you really need a name here with only 1?
Yes, cpufreq drivers need to dance around the genpd and OPP frameworks,
which requires a name.
Konrad
>
>> + };
>> +
>> + cpu@100 {
>> + compatible = "qcom,kryo280";
>> + device_type = "cpu";
>> + reg = <0x0 0x100>;
>> + operating-points-v2 = <&cpu4_opp_table>;
>> + power-domains = <&apc_cprh 1>;
>> + power-domain-names = "cprh";
>> + };
>> + };
>> +
>> + cpu0_opp_table: opp-table-cpu0 {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp-1843200000 {
>> + opp-hz = /bits/ 64 <1843200000>;
>> + required-opps = <&cprh_opp3>;
>> + };
>> +
>> + opp-1094400000 {
>> + opp-hz = /bits/ 64 <1094400000>;
>> + required-opps = <&cprh_opp2>;
>> + };
>> +
>> + opp-300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + required-opps = <&cprh_opp1>;
>> + };
>> + };
>> +
>> + cpu4_opp_table: opp-table-cpu4 {
>> + compatible = "operating-points-v2";
>> + opp-shared;
>> +
>> + opp-2208000000 {
>> + opp-hz = /bits/ 64 <2208000000>;
>> + required-opps = <&cprh_opp3>;
>> + };
>> +
>> + opp-1113600000 {
>> + opp-hz = /bits/ 64 <1113600000>;
>> + required-opps = <&cprh_opp2>;
>> + };
>> +
>> + opp-300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + required-opps = <&cprh_opp1>;
>> + };
>> + };
>> +
>> + cprh_opp_table: opp-table-cprh {
>> + compatible = "operating-points-v2-qcom-level";
>> +
>> + cprh_opp1: opp-1 {
>> + opp-level = <1>;
>> + qcom,opp-fuse-level = <1>;
>> + qcom,opp-cloop-vadj = <0>;
>> + qcom,opp-oloop-vadj = <0>;
>> + };
>> +
>> + cprh_opp2: opp-2 {
>> + opp-level = <2>;
>> + qcom,opp-fuse-level = <2>;
>> + qcom,opp-cloop-vadj = <0>;
>> + qcom,opp-oloop-vadj = <0>;
>> + };
>> +
>> + cprh_opp3: opp-3 {
>> + opp-level = <3>;
>> + qcom,opp-fuse-level = <2 3>;
>> + qcom,opp-cloop-vadj = <0>;
>> + qcom,opp-oloop-vadj = <0>;
>> + };
>> + };
>> +
>> + apc_cprh: power-controller@179c8000 {
>> + compatible = "qcom,msm8998-cprh", "qcom,cprh";
>> + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
>> + clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
>> +
>> + operating-points-v2 = <&cprh_opp_table>;
>> + #power-domain-cells = <1>;
>> +
>> + nvmem-cells = <&cpr_efuse_speedbin>,
>> + <&cpr_fuse_revision>,
>> + <&cpr_quot0_pwrcl>,
>> + <&cpr_quot1_pwrcl>,
>> + <&cpr_quot2_pwrcl>,
>> + <&cpr_quot3_pwrcl>,
>> + <&cpr_quot_offset1_pwrcl>,
>> + <&cpr_quot_offset2_pwrcl>,
>> + <&cpr_quot_offset3_pwrcl>,
>> + <&cpr_init_voltage0_pwrcl>,
>> + <&cpr_init_voltage1_pwrcl>,
>> + <&cpr_init_voltage2_pwrcl>,
>> + <&cpr_init_voltage3_pwrcl>,
>> + <&cpr_ro_sel0_pwrcl>,
>> + <&cpr_ro_sel1_pwrcl>,
>> + <&cpr_ro_sel2_pwrcl>,
>> + <&cpr_ro_sel3_pwrcl>,
>> + <&cpr_quot0_perfcl>,
>> + <&cpr_quot1_perfcl>,
>> + <&cpr_quot2_perfcl>,
>> + <&cpr_quot3_perfcl>,
>> + <&cpr_quot_offset1_perfcl>,
>> + <&cpr_quot_offset2_perfcl>,
>> + <&cpr_quot_offset3_perfcl>,
>> + <&cpr_init_voltage0_perfcl>,
>> + <&cpr_init_voltage1_perfcl>,
>> + <&cpr_init_voltage2_perfcl>,
>> + <&cpr_init_voltage3_perfcl>,
>> + <&cpr_ro_sel0_perfcl>,
>> + <&cpr_ro_sel1_perfcl>,
>> + <&cpr_ro_sel2_perfcl>,
>> + <&cpr_ro_sel3_perfcl>;
>> + nvmem-cell-names = "cpr_speed_bin",
>> + "cpr_fuse_revision",
>> + "cpr0_quotient1",
>> + "cpr0_quotient2",
>> + "cpr0_quotient3",
>> + "cpr0_quotient4",
>> + "cpr0_quotient_offset2",
>> + "cpr0_quotient_offset3",
>> + "cpr0_quotient_offset4",
>> + "cpr0_init_voltage1",
>> + "cpr0_init_voltage2",
>> + "cpr0_init_voltage3",
>> + "cpr0_init_voltage4",
>> + "cpr0_ring_osc1",
>> + "cpr0_ring_osc2",
>> + "cpr0_ring_osc3",
>> + "cpr0_ring_osc4",
>> + "cpr1_quotient1",
>> + "cpr1_quotient2",
>> + "cpr1_quotient3",
>> + "cpr1_quotient4",
>> + "cpr1_quotient_offset2",
>> + "cpr1_quotient_offset3",
>> + "cpr1_quotient_offset4",
>> + "cpr1_init_voltage1",
>> + "cpr1_init_voltage2",
>> + "cpr1_init_voltage3",
>> + "cpr1_init_voltage4",
>> + "cpr1_ring_osc1",
>> + "cpr1_ring_osc2",
>> + "cpr1_ring_osc3",
>> + "cpr1_ring_osc4";
>> + };
>> +...
>>
>> --
>> 2.41.0
>>
new file mode 100644
@@ -0,0 +1,289 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh)
+
+description:
+ CPR (Core Power Reduction) is a technology to reduce core power of a CPU
+ (or another device). Each OPP of a device corresponds to a "corner" that
+ has a range of valid voltages for a particular frequency.
+ The CPR monitors dynamic factors such as temperature, etc. and suggests
+ or (in the CPR-hardened case) applies voltage adjustments to save power
+ and meet silicon characteristic requirements for a given chip unit.
+
+maintainers:
+ - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+properties:
+ compatible:
+ oneOf:
+ - description: CPRv3 controller
+ items:
+ - const: qcom,cpr3
+ - description: CPRv4 controller
+ items:
+ - const: qcom,cpr4
+ - description: CPRv4-Hardened controller
+ items:
+ - enum:
+ - qcom,msm8998-cprh
+ - qcom,sdm630-cprh
+ - const: qcom,cprh
+
+ reg:
+ description: Base address and size of the CPR controller(s)
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: CPR reference clock
+
+ vdd-supply:
+ description: Autonomous Phase Control (APC) or other power supply
+
+ '#power-domain-cells':
+ const: 1
+
+ qcom,acc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to syscon for writing ACC settings
+
+ nvmem-cells:
+ description: Cells containing the fuse corners and revision data
+ maxItems: 32
+
+ nvmem-cell-names:
+ maxItems: 32
+
+ operating-points-v2: true
+
+ power-domains: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - operating-points-v2
+ - "#power-domain-cells"
+ - nvmem-cells
+ - nvmem-cell-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-cprh
+ then:
+ properties:
+ nvmem-cell-names:
+ items:
+ - const: cpr_speed_bin
+ - const: cpr_fuse_revision
+ - const: cpr0_quotient1
+ - const: cpr0_quotient2
+ - const: cpr0_quotient3
+ - const: cpr0_quotient4
+ - const: cpr0_quotient_offset2
+ - const: cpr0_quotient_offset3
+ - const: cpr0_quotient_offset4
+ - const: cpr0_init_voltage1
+ - const: cpr0_init_voltage2
+ - const: cpr0_init_voltage3
+ - const: cpr0_init_voltage4
+ - const: cpr0_ring_osc1
+ - const: cpr0_ring_osc2
+ - const: cpr0_ring_osc3
+ - const: cpr0_ring_osc4
+ - const: cpr1_quotient1
+ - const: cpr1_quotient2
+ - const: cpr1_quotient3
+ - const: cpr1_quotient4
+ - const: cpr1_quotient_offset2
+ - const: cpr1_quotient_offset3
+ - const: cpr1_quotient_offset4
+ - const: cpr1_init_voltage1
+ - const: cpr1_init_voltage2
+ - const: cpr1_init_voltage3
+ - const: cpr1_init_voltage4
+ - const: cpr1_ring_osc1
+ - const: cpr1_ring_osc2
+ - const: cpr1_ring_osc3
+ - const: cpr1_ring_osc4
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "qcom,kryo280";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ power-domains = <&apc_cprh 0>;
+ power-domain-names = "cprh";
+ };
+
+ cpu@100 {
+ compatible = "qcom,kryo280";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ operating-points-v2 = <&cpu4_opp_table>;
+ power-domains = <&apc_cprh 1>;
+ power-domain-names = "cprh";
+ };
+ };
+
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1843200000 {
+ opp-hz = /bits/ 64 <1843200000>;
+ required-opps = <&cprh_opp3>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ required-opps = <&cprh_opp2>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ required-opps = <&cprh_opp3>;
+ };
+
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ required-opps = <&cprh_opp2>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&cprh_opp1>;
+ };
+ };
+
+ cprh_opp_table: opp-table-cprh {
+ compatible = "operating-points-v2-qcom-level";
+
+ cprh_opp1: opp-1 {
+ opp-level = <1>;
+ qcom,opp-fuse-level = <1>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cprh_opp2: opp-2 {
+ opp-level = <2>;
+ qcom,opp-fuse-level = <2>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+
+ cprh_opp3: opp-3 {
+ opp-level = <3>;
+ qcom,opp-fuse-level = <2 3>;
+ qcom,opp-cloop-vadj = <0>;
+ qcom,opp-oloop-vadj = <0>;
+ };
+ };
+
+ apc_cprh: power-controller@179c8000 {
+ compatible = "qcom,msm8998-cprh", "qcom,cprh";
+ reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>;
+ clocks = <&gcc GCC_HMSS_RBCPR_CLK>;
+
+ operating-points-v2 = <&cprh_opp_table>;
+ #power-domain-cells = <1>;
+
+ nvmem-cells = <&cpr_efuse_speedbin>,
+ <&cpr_fuse_revision>,
+ <&cpr_quot0_pwrcl>,
+ <&cpr_quot1_pwrcl>,
+ <&cpr_quot2_pwrcl>,
+ <&cpr_quot3_pwrcl>,
+ <&cpr_quot_offset1_pwrcl>,
+ <&cpr_quot_offset2_pwrcl>,
+ <&cpr_quot_offset3_pwrcl>,
+ <&cpr_init_voltage0_pwrcl>,
+ <&cpr_init_voltage1_pwrcl>,
+ <&cpr_init_voltage2_pwrcl>,
+ <&cpr_init_voltage3_pwrcl>,
+ <&cpr_ro_sel0_pwrcl>,
+ <&cpr_ro_sel1_pwrcl>,
+ <&cpr_ro_sel2_pwrcl>,
+ <&cpr_ro_sel3_pwrcl>,
+ <&cpr_quot0_perfcl>,
+ <&cpr_quot1_perfcl>,
+ <&cpr_quot2_perfcl>,
+ <&cpr_quot3_perfcl>,
+ <&cpr_quot_offset1_perfcl>,
+ <&cpr_quot_offset2_perfcl>,
+ <&cpr_quot_offset3_perfcl>,
+ <&cpr_init_voltage0_perfcl>,
+ <&cpr_init_voltage1_perfcl>,
+ <&cpr_init_voltage2_perfcl>,
+ <&cpr_init_voltage3_perfcl>,
+ <&cpr_ro_sel0_perfcl>,
+ <&cpr_ro_sel1_perfcl>,
+ <&cpr_ro_sel2_perfcl>,
+ <&cpr_ro_sel3_perfcl>;
+ nvmem-cell-names = "cpr_speed_bin",
+ "cpr_fuse_revision",
+ "cpr0_quotient1",
+ "cpr0_quotient2",
+ "cpr0_quotient3",
+ "cpr0_quotient4",
+ "cpr0_quotient_offset2",
+ "cpr0_quotient_offset3",
+ "cpr0_quotient_offset4",
+ "cpr0_init_voltage1",
+ "cpr0_init_voltage2",
+ "cpr0_init_voltage3",
+ "cpr0_init_voltage4",
+ "cpr0_ring_osc1",
+ "cpr0_ring_osc2",
+ "cpr0_ring_osc3",
+ "cpr0_ring_osc4",
+ "cpr1_quotient1",
+ "cpr1_quotient2",
+ "cpr1_quotient3",
+ "cpr1_quotient4",
+ "cpr1_quotient_offset2",
+ "cpr1_quotient_offset3",
+ "cpr1_quotient_offset4",
+ "cpr1_init_voltage1",
+ "cpr1_init_voltage2",
+ "cpr1_init_voltage3",
+ "cpr1_init_voltage4",
+ "cpr1_ring_osc1",
+ "cpr1_ring_osc2",
+ "cpr1_ring_osc3",
+ "cpr1_ring_osc4";
+ };
+...