diff mbox series

[V2,19/21] RISC-V: Enable ACPI in defconfig

Message ID	20230216182043.1946553-20-sunilvl@ventanamicro.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; From: Sunil V L <sunilvl@ventanamicro.com> To: Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Paul Walmsley <paul.walmsley@sifive.com>, "Rafael J . Wysocki" <rafael@kernel.org>, Len Brown <lenb@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Jonathan Corbet <corbet@lwn.net> Cc: linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Conor Dooley <conor.dooley@microchip.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <apatel@ventanamicro.com>, Atish Patra <atishp@rivosinc.com>, Sunil V L <sunilvl@ventanamicro.com>, "Rafael J . Wysocki" <rafael.j.wysocki@intel.com> Subject: [PATCH V2 19/21] RISC-V: Enable ACPI in defconfig Date: Thu, 16 Feb 2023 23:50:41 +0530 Message-Id: <20230216182043.1946553-20-sunilvl@ventanamicro.com> In-Reply-To: <20230216182043.1946553-1-sunilvl@ventanamicro.com> References: <20230216182043.1946553-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Add basic ACPI support for RISC-V \| [V2,00/21] Add basic ACPI support for RISC-V [V2,01/21] riscv: move sbi_init() earlier before jump_label_init() [V2,02/21] ACPICA: MADT: Add RISC-V INTC interrupt controller [V2,03/21] ACPICA: Add structure definitions for RISC-V RHCT [V2,04/21] RISC-V: Add support to build the ACPI core [V2,05/21] ACPI: Kconfig: Enable ACPI_PROCESSOR for RISC-V [V2,06/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V. [V2,07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid [V2,08/21] drivers/acpi: RISC-V: Add RHCT related code [V2,09/21] RISC-V: smpboot: Create wrapper smp_setup() [V2,10/21] RISC-V: smpboot: Add ACPI support in smp_setup() [V2,11/21] RISC-V: ACPI: Add a function to retrieve the hartid [V2,12/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() [V2,13/21] RISC-V: cpu: Enable cpuinfo for ACPI systems [V2,14/21] irqchip/riscv-intc: Add ACPI support [V2,15/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() [V2,16/21] clocksource/timer-riscv: Add ACPI support [V2,17/21] RISC-V: time.c: Add ACPI support for time_init() [V2,18/21] RISC-V: Add ACPI initialization in setup_arch() [V2,19/21] RISC-V: Enable ACPI in defconfig [V2,20/21] MAINTAINERS: Add entry for drivers/acpi/riscv [V2,21/21] Documentation/kernel-parameters.txt: Add RISC-V for ACPI parameter

Commit Message

Sunil V L Feb. 16, 2023, 6:20 p.m. UTC

  Add support to build ACPI subsystem in defconfig.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
 arch/riscv/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

Comments

Andrew Jones Feb. 20, 2023, 8:09 p.m. UTC | #1

On Thu, Feb 16, 2023 at 11:50:41PM +0530, Sunil V L wrote:
> Add support to build ACPI subsystem in defconfig.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
>  arch/riscv/configs/defconfig | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 128dcf4c0814..f89f79294b34 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -218,3 +218,5 @@ CONFIG_RCU_EQS_DEBUG=y
>  # CONFIG_FTRACE is not set
>  # CONFIG_RUNTIME_TESTING_MENU is not set
>  CONFIG_MEMTEST=y
> +CONFIG_ACPI=y
> +# CONFIG_PCI_QUIRKS is not set

I'm guessing the addition of the CONFIG_PCI_QUIRKS line wasn't
intentional?

> -- 
> 2.34.1
>

Thanks,
drew

Sunil V L Feb. 24, 2023, 8:46 a.m. UTC | #2

On Mon, Feb 20, 2023 at 09:09:09PM +0100, Andrew Jones wrote:
> On Thu, Feb 16, 2023 at 11:50:41PM +0530, Sunil V L wrote:
> > Add support to build ACPI subsystem in defconfig.
> > 
> > Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> > Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> > ---
> >  arch/riscv/configs/defconfig | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index 128dcf4c0814..f89f79294b34 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -218,3 +218,5 @@ CONFIG_RCU_EQS_DEBUG=y
> >  # CONFIG_FTRACE is not set
> >  # CONFIG_RUNTIME_TESTING_MENU is not set
> >  CONFIG_MEMTEST=y
> > +CONFIG_ACPI=y
> > +# CONFIG_PCI_QUIRKS is not set
> 
> I'm guessing the addition of the CONFIG_PCI_QUIRKS line wasn't
> intentional?
> 
Yes, I realized after sending the series. Will remove it in next
revision.

Thanks,
Sunil

diff mbox series

Patch

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 128dcf4c0814..f89f79294b34 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -218,3 +218,5 @@  CONFIG_RCU_EQS_DEBUG=y
 # CONFIG_FTRACE is not set
 # CONFIG_RUNTIME_TESTING_MENU is not set
 CONFIG_MEMTEST=y
+CONFIG_ACPI=y
+# CONFIG_PCI_QUIRKS is not set