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[2620:137:e000::1:20]) by mx.google.com with ESMTP id r12-20020a63440c000000b004fbacd1a872si11223559pga.853.2023.03.07.05.20.16; Tue, 07 Mar 2023 05:20:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MTRyrWkS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230203AbjCGNGB (ORCPT + 99 others); Tue, 7 Mar 2023 08:06:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230178AbjCGNFh (ORCPT ); Tue, 7 Mar 2023 08:05:37 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEDA0222D6 for ; Tue, 7 Mar 2023 05:05:06 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id g17so16984413lfv.4 for ; Tue, 07 Mar 2023 05:05:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678194292; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=c+tr96cZPYMIs0/699FeDkH9/3i8GidF6/NXAvTE8Kg=; b=MTRyrWkS7GsWcEkunnMBjIRdfCenrGT6pejPsQpaMjny1E9LxOLhNuYcmE63XcretE q32JKPriAzgizybVT2MdxJB81iYgmxx9BDGvO5sThBiHenSJ7TSi/mcCS7HV45kNSB+o nFuYaRyNuTrLB/gDQWIzcHqjGHC4nG+KIehAX49XQhAmP6StJuWO/emG5x7MtfyOBx9l GaidXtEecvBXnaThlgDQYyk6Tii4rSQ5+FWEGPJMgf0tXP/G8OvA1Q4Owy9fxFZtgjTS Z73ZjNA+ds7dyP6GQI9sn+6ttAPoCeqV+GNke2NCiS00Xz8TQ5J4gx5NG89RyXvxS8in LnRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678194292; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c+tr96cZPYMIs0/699FeDkH9/3i8GidF6/NXAvTE8Kg=; b=Tm1KTLmu7W0mKUf2aN1iOyPOYg+n4a/XDv0SAnrqI8JDvqjXNjyIMBGGRydck8poi6 ViuM1/unD5I4S0B+CYJwYM5lOJpEG2iab7G6++CtCbpmJ65ImbvgEWcwDmd96CJFoHlY J8SOjCNVyFpDWx1wbq1V+vLz7mEEGZFZQ1ePLM1RRiyM10fV/u0h0GhT0Q7Vg9M9H5NW 15yYLb56u1ktNv1zImQ9QMfvbmAXhz1+GsN2Q+MekxSoUhLilqTLBT4lSkvkQqTTJUKx gPnmhz1nyI++FHioWqfptZjOUu+aWd0+ObkyblKSmVlSP7+CDjKErIXKrR34JHN63c60 FssQ== X-Gm-Message-State: AO0yUKV/X0JBCvTXNT1Lvvoj4qmgRjOq5tFJu5QVwnWvd7PXYF+hMtqO TQWAGDucQ3FzbQOYq6o+TDjcig== X-Received: by 2002:ac2:5214:0:b0:4cb:4378:9c6 with SMTP id a20-20020ac25214000000b004cb437809c6mr3479109lfl.23.1678194292689; Tue, 07 Mar 2023 05:04:52 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.219]) by smtp.gmail.com with ESMTPSA id w14-20020ac2598e000000b004caf992bba9sm2030548lfn.268.2023.03.07.05.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:04:52 -0800 (PST) From: Linus Walleij Date: Tue, 07 Mar 2023 14:04:49 +0100 Subject: [PATCH v2 07/16] gpio: hisi: Convert to immutable irq_chip MIME-Version: 1.0 Message-Id: <20230215-immutable-chips-v2-7-d6b0e3f2d991@linaro.org> References: <20230215-immutable-chips-v2-0-d6b0e3f2d991@linaro.org> In-Reply-To: <20230215-immutable-chips-v2-0-d6b0e3f2d991@linaro.org> To: Mun Yew Tham , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Alban Bedel , Orson Zhai , Baolin Wang , Chunyan Zhang , Jay Fang , Daniel Palmer , Romain Perier , Santosh Shilimkar , Kevin Hilman , William Breathitt Gray Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-omap@vger.kernel.org, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759715240677057982?= X-GMAIL-MSGID: =?utf-8?q?1759715240677057982?= Convert the driver to immutable irq-chip with a bit of intuition. The IRQ chip was unnamed which seems unwise, so we just assign the name "HISI-GPIO". Cc: Marc Zyngier Acked-by: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/gpio/gpio-hisi.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpio/gpio-hisi.c b/drivers/gpio/gpio-hisi.c index 55bd69043bf4..29a03de37fd8 100644 --- a/drivers/gpio/gpio-hisi.c +++ b/drivers/gpio/gpio-hisi.c @@ -37,7 +37,6 @@ struct hisi_gpio { struct device *dev; void __iomem *reg_base; unsigned int line_num; - struct irq_chip irq_chip; int irq; }; @@ -100,12 +99,14 @@ static void hisi_gpio_irq_set_mask(struct irq_data *d) struct gpio_chip *chip = irq_data_get_irq_chip_data(d); hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d))); + gpiochip_disable_irq(chip, irqd_to_hwirq(d)); } static void hisi_gpio_irq_clr_mask(struct irq_data *d) { struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + gpiochip_enable_irq(chip, irqd_to_hwirq(d)); hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d))); } @@ -191,20 +192,24 @@ static void hisi_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(irq_c, desc); } +static const struct irq_chip hisi_gpio_irq_chip = { + .name = "HISI-GPIO", + .irq_ack = hisi_gpio_set_ack, + .irq_mask = hisi_gpio_irq_set_mask, + .irq_unmask = hisi_gpio_irq_clr_mask, + .irq_set_type = hisi_gpio_irq_set_type, + .irq_enable = hisi_gpio_irq_enable, + .irq_disable = hisi_gpio_irq_disable, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio) { struct gpio_chip *chip = &hisi_gpio->chip; struct gpio_irq_chip *girq_chip = &chip->irq; - /* Set hooks for irq_chip */ - hisi_gpio->irq_chip.irq_ack = hisi_gpio_set_ack; - hisi_gpio->irq_chip.irq_mask = hisi_gpio_irq_set_mask; - hisi_gpio->irq_chip.irq_unmask = hisi_gpio_irq_clr_mask; - hisi_gpio->irq_chip.irq_set_type = hisi_gpio_irq_set_type; - hisi_gpio->irq_chip.irq_enable = hisi_gpio_irq_enable; - hisi_gpio->irq_chip.irq_disable = hisi_gpio_irq_disable; - - girq_chip->chip = &hisi_gpio->irq_chip; + gpio_irq_chip_set_chip(girq_chip, &hisi_gpio_irq_chip); girq_chip->default_type = IRQ_TYPE_NONE; girq_chip->num_parents = 1; girq_chip->parents = &hisi_gpio->irq;