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[2620:137:e000::1:20]) by mx.google.com with ESMTP id kn15-20020a170903078f00b0019a96849d6dsi6032988plb.605.2023.03.07.05.20.03; Tue, 07 Mar 2023 05:20:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xFEOAYGu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbjCGNFv (ORCPT + 99 others); Tue, 7 Mar 2023 08:05:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230143AbjCGNFb (ORCPT ); Tue, 7 Mar 2023 08:05:31 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C0E37B481 for ; Tue, 7 Mar 2023 05:05:00 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id r27so16941576lfe.10 for ; Tue, 07 Mar 2023 05:05:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678194288; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=b0p5EbpuJP6hwcjXoMYtiND4JppiiLVgXD+CFpX3rE4=; b=xFEOAYGuIoPsxPVhSwnYu52ahL7geiD4JVsX78tkiKB0nDxX66O85TkmquqlMnV3Cf KFT9X4bqt5tlWpqJAvS5nYwxT8BHqoEvAJLGm07IPzLBcFnoUfUsxg2mF5Bh7UxTpmcY br0YeIBO98Hp3nNOFbKpVqEqKRqnlIFsR0xn2ggRhWM1OOw0tzyYYawGXjt8jdbc8tP9 EJZOC7XmbmHahw2Q/qcEC1YKAtlX49HY9TO16gaaJt6v1uDqU55HClT+gx6G5+/3mLaQ Kb94zbPBynfFJXDzuqWS4ulOsWjA61IsdxelOB/Cc8MSGiAMkj8fP5wzey3fV3vui+RG 1pkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678194288; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b0p5EbpuJP6hwcjXoMYtiND4JppiiLVgXD+CFpX3rE4=; b=rrRi9kGUhBHOVG3MLLPJH2eNxD3Pw3EsQg6Uq13TAhGgg1tdhUYoQfiW9KXUsk4Gup doBnV8Q4wG/XFvHELnJWqkv0iizb8fyc62Rg1em9qKBmgPuoD9jJNBKgOUzydLHzIiAi /4tpxpXqfFNetwFCdmewoqP0UuXbeHujGrE70oOLs/mhrAxl2wOoKfj8qz+N98NJsqs7 HjyRppzi8pAxVlI0Wr/YqOcWE/JmE4HZkmchg9LWOv/Y8hEeoJq2dJ/WKY3xEfP8+kMN u2GBfEPNIbsgO9Bz/Ivwr9+WaD1L/C9w7kdnk0BhhmNvSbvJoSclMq4i5zECliV0oSyP Ki6g== X-Gm-Message-State: AO0yUKV1+xrN+f2YD5iC0/gVQe6uMnL3geiPJb2pZxiFIu/gHjE9bv2x Qun8NTuWdnrtyi1fHatv9FUVag== X-Received: by 2002:ac2:551d:0:b0:4dd:9a38:fcc with SMTP id j29-20020ac2551d000000b004dd9a380fccmr3973440lfk.63.1678194288471; Tue, 07 Mar 2023 05:04:48 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.219]) by smtp.gmail.com with ESMTPSA id w14-20020ac2598e000000b004caf992bba9sm2030548lfn.268.2023.03.07.05.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 05:04:48 -0800 (PST) From: Linus Walleij Date: Tue, 07 Mar 2023 14:04:45 +0100 Subject: [PATCH v2 03/16] gpio: aspeed: Convert to immutable irq_chip MIME-Version: 1.0 Message-Id: <20230215-immutable-chips-v2-3-d6b0e3f2d991@linaro.org> References: <20230215-immutable-chips-v2-0-d6b0e3f2d991@linaro.org> In-Reply-To: <20230215-immutable-chips-v2-0-d6b0e3f2d991@linaro.org> To: Mun Yew Tham , Bartosz Golaszewski , Joel Stanley , Andrew Jeffery , Alban Bedel , Orson Zhai , Baolin Wang , Chunyan Zhang , Jay Fang , Daniel Palmer , Romain Perier , Santosh Shilimkar , Kevin Hilman , William Breathitt Gray Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-omap@vger.kernel.org, Linus Walleij , Marc Zyngier X-Mailer: b4 0.12.1 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759715226262091140?= X-GMAIL-MSGID: =?utf-8?q?1759715226262091140?= Convert the driver to immutable irq-chip with a bit of intuition. Cc: Marc Zyngier Tested-by: Joel Stanley Acked-by: Marc Zyngier Signed-off-by: Linus Walleij --- drivers/gpio/gpio-aspeed.c | 44 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index a94da80d3a95..9c4852de2733 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -53,7 +54,7 @@ struct aspeed_gpio_config { */ struct aspeed_gpio { struct gpio_chip chip; - struct irq_chip irqc; + struct device *dev; raw_spinlock_t lock; void __iomem *base; int irq; @@ -566,6 +567,10 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) addr = bank_reg(gpio, bank, reg_irq_enable); + /* Unmasking the IRQ */ + if (set) + gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); + raw_spin_lock_irqsave(&gpio->lock, flags); copro = aspeed_gpio_copro_request(gpio, offset); @@ -579,6 +584,10 @@ static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) if (copro) aspeed_gpio_copro_release(gpio, offset); raw_spin_unlock_irqrestore(&gpio->lock, flags); + + /* Masking the IRQ */ + if (!set) + gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); } static void aspeed_gpio_irq_mask(struct irq_data *d) @@ -1080,6 +1089,30 @@ int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) } EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); +static void aspeed_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) +{ + const struct aspeed_gpio_bank *bank; + struct aspeed_gpio *gpio; + u32 bit; + int rc, offset; + + rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); + if (rc) + return; + + seq_printf(p, dev_name(gpio->dev)); +} + +static const struct irq_chip aspeed_gpio_irq_chip = { + .irq_ack = aspeed_gpio_irq_ack, + .irq_mask = aspeed_gpio_irq_mask, + .irq_unmask = aspeed_gpio_irq_unmask, + .irq_set_type = aspeed_gpio_set_type, + .irq_print_chip = aspeed_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + /* * Any banks not specified in a struct aspeed_bank_props array are assumed to * have the properties: @@ -1149,6 +1182,8 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) if (IS_ERR(gpio->base)) return PTR_ERR(gpio->base); + gpio->dev = &pdev->dev; + raw_spin_lock_init(&gpio->lock); gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); @@ -1208,12 +1243,9 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) gpio->irq = rc; girq = &gpio->chip.irq; - girq->chip = &gpio->irqc; + gpio_irq_chip_set_chip(girq, &aspeed_gpio_irq_chip); girq->chip->name = dev_name(&pdev->dev); - girq->chip->irq_ack = aspeed_gpio_irq_ack; - girq->chip->irq_mask = aspeed_gpio_irq_mask; - girq->chip->irq_unmask = aspeed_gpio_irq_unmask; - girq->chip->irq_set_type = aspeed_gpio_set_type; + girq->parent_handler = aspeed_gpio_irq_handler; girq->num_parents = 1; girq->parents = devm_kcalloc(&pdev->dev, 1,