Message ID | 20230214234426.344960-2-jithu.joseph@intel.com |
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State | New |
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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s22-20020a170906221600b008b13afdbdefsi1752160ejs.822.2023.02.14.15.49.26; Tue, 14 Feb 2023 15:49:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=TibgpoaU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232720AbjBNXp6 (ORCPT <rfc822;tebrre53rla2o@gmail.com> + 99 others); Tue, 14 Feb 2023 18:45:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229725AbjBNXp4 (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Tue, 14 Feb 2023 18:45:56 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44FCC2CC42; Tue, 14 Feb 2023 15:45:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676418355; x=1707954355; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RJlwSFVpT1cewwIwRvUfBxfg5OygWbxR/zFOIt+ZgzQ=; b=TibgpoaUuRq5ZSm+amD9pUoPlf57cAzpVsHfNiYJEYNJFvEHO0Mr2Ijj XWYj4GqGiinoLsXETGizxqyVLlI3wRBp+iM7xhDgmXPOFTjelyoEYbUZ3 1CwvhpHeEsykdvBraNpVWdmdMfPcNF3LQKnicj7y8GRxgduu0yi4I8PYf XsX+Mvt3db+S9vgiwB6iIFAYt/m2JclUmcZkxj09rcoA6/te3JI0smBFC OWH9B5XibHvVQpcvCPIlwkvBwwU48GbhFnfuZ/AuWnP6ouw67KA6+nFrv qB9XVCwE86qhFGXoTH4wsWu2clxlJthdeoTEbhq8OqSw96O06ctyprbm/ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10621"; a="417522992" X-IronPort-AV: E=Sophos;i="5.97,298,1669104000"; d="scan'208";a="417522992" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2023 15:45:54 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10621"; a="669391008" X-IronPort-AV: E=Sophos;i="5.97,298,1669104000"; d="scan'208";a="669391008" Received: from jithujos.sc.intel.com ([172.25.103.66]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2023 15:45:53 -0800 From: Jithu Joseph <jithu.joseph@intel.com> To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH v2 1/7] x86/include/asm/msr-index.h: Add IFS Array test bits Date: Tue, 14 Feb 2023 15:44:20 -0800 Message-Id: <20230214234426.344960-2-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214234426.344960-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> <20230214234426.344960-1-jithu.joseph@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756583687208982608?= X-GMAIL-MSGID: =?utf-8?q?1757852302583457395?= |
Series |
Add Array BIST test support to IFS
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Commit Message
Jithu Joseph
Feb. 14, 2023, 11:44 p.m. UTC
Define MSR bitfields for enumerating support for Array BIST test. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d3fe82c5d6b6..ad8997773ad3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -197,6 +197,8 @@ /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ #define MSR_INTEGRITY_CAPS 0x000002d9 +#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 +#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT)