[2/3] arm64: dts: qcom: sa8775p: add the SPI node for sa8775p-ride
Commit Message
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Add the SPI node for the interface exposed on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 14 ++++++++++++++
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 21 +++++++++++++++++++++
2 files changed, 35 insertions(+)
@@ -14,6 +14,7 @@ / {
aliases {
serial0 = &uart10;
i2c18 = &i2c18;
+ spi16 = &spi16;
};
chosen {
@@ -40,12 +41,25 @@ &sleep_clk {
clock-frequency = <32764>;
};
+&spi16 {
+ pinctrl-0 = <&qup_spi16_default>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
&tlmm {
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
};
+ qup_spi16_default: qup-spi16-state {
+ pins = "gpio86", "gpio87", "gpio88", "gpio89";
+ function = "qup2_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_i2c18_default: qup-i2c18-state {
pins = "gpio95", "gpio96";
function = "qup2_se4";
@@ -503,6 +503,27 @@ qupv3_id_2: geniqup@8c0000 {
iommus = <&apps_smmu 0x5a3 0x0>;
status = "disabled";
+ spi16: spi@888000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x888000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
+ clock-names = "se";
+ interconnects = <&clk_virt MASTER_QUP_CORE_2 0
+ &clk_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_APPSS_PROC 0
+ &config_noc SLAVE_QUP_2 0>,
+ <&aggre2_noc MASTER_QUP_2 0
+ &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+ power-domains = <&rpmhpd SA8775P_CX>;
+ status = "disabled";
+ };
+
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x890000 0x0 0x4000>;