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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n14-20020a170903110e00b001945ff85d7asi14742331plh.357.2023.02.13.19.14.14; Mon, 13 Feb 2023 19:14:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=MTotiJc7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229686AbjBNDNd (ORCPT + 99 others); Mon, 13 Feb 2023 22:13:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230175AbjBNDNb (ORCPT ); Mon, 13 Feb 2023 22:13:31 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE7B21C5B1; Mon, 13 Feb 2023 19:13:09 -0800 (PST) X-UUID: 7ee20e1cac1511ed945fc101203acc17-20230214 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+EGLUaBC3v82VSRXlNpepa3rCVLx+JRYT7AbHzxDeSE=; b=MTotiJc7rt83ZHV0ZAuRqqZJY3sBA3CvZ9sDnuqlXpDzZjeYiWf3b0offHwanmSepuZLGx2vnamqCuzWNyv+l6YkaXgd/ccKfniodl2fjkP+QQu4dwdIqUy6GDZE4i394qy885X7Ibp4+SQuWwIcgNQ2hTDH/9thhv+Y0fuGXvE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.19,REQID:bcdb5710-008b-46a2-8aae-d7ddf089a7d8,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.19,REQID:bcdb5710-008b-46a2-8aae-d7ddf089a7d8,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:885ddb2,CLOUDID:38d15bf8-ff42-4fb0-b929-626456a83c14,B ulkID:230214111306B7Z4KBDL,BulkQuantity:0,Recheck:0,SF:38|29|28|17|19|48,T C:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 ,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: 7ee20e1cac1511ed945fc101203acc17-20230214 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1923575240; Tue, 14 Feb 2023 11:13:04 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 14 Feb 2023 11:13:02 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 14 Feb 2023 11:13:01 +0800 From: Yong Wu To: Joerg Roedel , Matthias Brugger , Mauro Carvalho Chehab , Rob Herring CC: Will Deacon , Robin Murphy , Krzysztof Kozlowski , Hans Verkuil , , , , , , , , AngeloGioacchino Del Regno , , , , Yunfei Dong , kyrie wu , , , , Yong Wu Subject: [PATCH v3 08/11] iommu/mediatek: Add a gap for the iova regions Date: Tue, 14 Feb 2023 11:11:11 +0800 Message-ID: <20230214031114.926-9-yong.wu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230214031114.926-1-yong.wu@mediatek.com> References: <20230214031114.926-1-yong.wu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757774575061854856?= X-GMAIL-MSGID: =?utf-8?q?1757774575061854856?= As the removed property in the vcodec dt-binding, the property is: dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; The length is 0xfff0_0000 rather than 0x1_0000_0000, this means it requires 1M as a gap. This is because the end address for some vcodec HW is (address + size). If the size is 4G, the end address may be 0x2_0000_0000, and the width for vcodec register only is 32, then the HW may get the ZERO address. Currently the consumer's dma-ranges property doesn't work, IOMMU has to consider this case. Add a bigger gap(8M) for all the regions to avoid it. Signed-off-by: Yong Wu Reviewed-by: AngeloGioacchino Del Regno --- drivers/iommu/mtk_iommu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 995e59cabf6c..4503fba72384 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -329,7 +329,7 @@ static LIST_HEAD(m4ulist); /* List all the M4U HWs */ #define for_each_m4u(data, head) list_for_each_entry(data, head, list) static const struct mtk_iommu_iova_region single_domain[] = { - {.iova_base = 0, .size = SZ_4G}, + {.iova_base = 0, .size = SZ_4G - SZ_8M}, }; #define MT8192_MULTI_REGION_MAX_NR 6 @@ -338,11 +338,11 @@ static const struct mtk_iommu_iova_region single_domain[] = { MT8192_MULTI_REGION_MAX_NR : 1) static const struct mtk_iommu_iova_region mt8192_multi_dom[MT8192_MULTI_REGION_NR] = { - { .iova_base = 0x0, .size = SZ_4G}, /* 0 ~ 4G */ + { .iova_base = 0x0, .size = SZ_4G - SZ_8M}, /* 0 ~ 4G, 8M as a gap. */ #if IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) - { .iova_base = SZ_4G, .size = SZ_4G}, /* 4G ~ 8G */ - { .iova_base = SZ_4G * 2, .size = SZ_4G}, /* 8G ~ 12G */ - { .iova_base = SZ_4G * 3, .size = SZ_4G}, /* 12G ~ 16G */ + { .iova_base = SZ_4G, .size = SZ_4G - SZ_8M}, /* 4G ~ 8G */ + { .iova_base = SZ_4G * 2, .size = SZ_4G - SZ_8M}, /* 8G ~ 12G */ + { .iova_base = SZ_4G * 3, .size = SZ_4G - SZ_8M}, /* 12G ~ 16G */ { .iova_base = 0x240000000ULL, .size = 0x4000000}, /* CCU0 */ { .iova_base = 0x244000000ULL, .size = 0x4000000}, /* CCU1 */