diff mbox series

[2/2] clk: qcom: clk-hfpll: switch to .determine_rate

Message ID 20230212-clk-qcom-determine_rate-v1-2-b4e447d4926e@z3ntu.xyz
State New
Headers
Series Switch hfpll & krait clock drivers to .determine_rate |

Commit Message

Luca Weiss Feb. 12, 2023, 2:11 p.m. UTC 
  .determine_rate is meant to replace .round_rate. The former comes with a
benefit which is especially relevant on 32-bit systems: since
.determine_rate uses an "unsigned long" (compared to a "signed long"
which is used by .round_rate) the maximum value on 32-bit systems
increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 drivers/clk/qcom/clk-hfpll.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Christian Marangi Feb. 12, 2023, 9:09 a.m. UTC | #1 
On Sun, Feb 12, 2023 at 03:11:09PM +0100, Luca Weiss wrote:
> .determine_rate is meant to replace .round_rate. The former comes with a
> benefit which is especially relevant on 32-bit systems: since
> .determine_rate uses an "unsigned long" (compared to a "signed long"
> which is used by .round_rate) the maximum value on 32-bit systems
> increases from 2^31 (or approx. 2.14GHz) to 2^32 (or approx. 4.29GHz).
> 
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>

Tested-by: Christian Marangi <ansuelsmth@gmail.com>

> ---
>  drivers/clk/qcom/clk-hfpll.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
> index 7dd17c184b69..86f728dc69e5 100644
> --- a/drivers/clk/qcom/clk-hfpll.c
> +++ b/drivers/clk/qcom/clk-hfpll.c
> @@ -128,20 +128,20 @@ static void clk_hfpll_disable(struct clk_hw *hw)
>  	spin_unlock_irqrestore(&h->lock, flags);
>  }
>  
> -static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
> -				 unsigned long *parent_rate)
> +static int clk_hfpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
>  {
>  	struct clk_hfpll *h = to_clk_hfpll(hw);
>  	struct hfpll_data const *hd = h->d;
>  	unsigned long rrate;
>  
> -	rate = clamp(rate, hd->min_rate, hd->max_rate);
> +	req->rate = clamp(req->rate, hd->min_rate, hd->max_rate);
>  
> -	rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
> +	rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate;
>  	if (rrate > hd->max_rate)
> -		rrate -= *parent_rate;
> +		rrate -= req->best_parent_rate;
>  
> -	return rrate;
> +	req->rate = rrate;
> +	return 0;
>  }
>  
>  /*
> @@ -241,7 +241,7 @@ const struct clk_ops clk_ops_hfpll = {
>  	.enable = clk_hfpll_enable,
>  	.disable = clk_hfpll_disable,
>  	.is_enabled = hfpll_is_enabled,
> -	.round_rate = clk_hfpll_round_rate,
> +	.determine_rate = clk_hfpll_determine_rate,
>  	.set_rate = clk_hfpll_set_rate,
>  	.recalc_rate = clk_hfpll_recalc_rate,
>  	.init = clk_hfpll_init,
> 
> -- 
> 2.39.1
>
diff mbox series

Patch

diff --git a/drivers/clk/qcom/clk-hfpll.c b/drivers/clk/qcom/clk-hfpll.c
index 7dd17c184b69..86f728dc69e5 100644
--- a/drivers/clk/qcom/clk-hfpll.c
+++ b/drivers/clk/qcom/clk-hfpll.c
@@ -128,20 +128,20 @@  static void clk_hfpll_disable(struct clk_hw *hw)
 	spin_unlock_irqrestore(&h->lock, flags);
 }
 
-static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
-				 unsigned long *parent_rate)
+static int clk_hfpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
 {
 	struct clk_hfpll *h = to_clk_hfpll(hw);
 	struct hfpll_data const *hd = h->d;
 	unsigned long rrate;
 
-	rate = clamp(rate, hd->min_rate, hd->max_rate);
+	req->rate = clamp(req->rate, hd->min_rate, hd->max_rate);
 
-	rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
+	rrate = DIV_ROUND_UP(req->rate, req->best_parent_rate) * req->best_parent_rate;
 	if (rrate > hd->max_rate)
-		rrate -= *parent_rate;
+		rrate -= req->best_parent_rate;
 
-	return rrate;
+	req->rate = rrate;
+	return 0;
 }
 
 /*
@@ -241,7 +241,7 @@  const struct clk_ops clk_ops_hfpll = {
 	.enable = clk_hfpll_enable,
 	.disable = clk_hfpll_disable,
 	.is_enabled = hfpll_is_enabled,
-	.round_rate = clk_hfpll_round_rate,
+	.determine_rate = clk_hfpll_determine_rate,
 	.set_rate = clk_hfpll_set_rate,
 	.recalc_rate = clk_hfpll_recalc_rate,
 	.init = clk_hfpll_init,