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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Emil Renner Berthing , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , Maxime Coquelin , Richard Cochran , Sagar Kadam , Yanhong Wang Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-riscv@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH 10/12] riscv: dts: starfive: jh7100: Add ccache DT node Date: Sat, 11 Feb 2023 05:18:19 +0200 Message-Id: <20230211031821.976408-11-cristian.ciocaltea@collabora.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> References: <20230211031821.976408-1-cristian.ciocaltea@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757503217523682982?= X-GMAIL-MSGID: =?utf-8?q?1757503217523682982?= Provide a DT node for the Sifive Composable Cache controller found on the StarFive JH7100 SoC. Note this is also used to support non-coherent DMA. Signed-off-by: Cristian Ciocaltea --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 7109e70fdab8..88f91bc5753b 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -32,6 +32,7 @@ U74_0: cpu@0 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; tlb-split; @@ -57,6 +58,7 @@ U74_1: cpu@1 { i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; tlb-split; @@ -116,6 +118,20 @@ soc { ranges; dma-noncoherent; + ccache: cache-controller@2010000 { + compatible = "starfive,jh7100-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>, + <0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + interrupts = <128>, <130>, <131>, <129>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + uncached-offset = <0xf 0x80000000>; + }; + clint: clint@2000000 { compatible = "starfive,jh7100-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0x10000>;