[v5,12/12] arm64: dts: mediatek: mt8195: Add SCP 2nd core
Commit Message
Rewrite the MT8195 SCP device node as a cluster and
add the SCP 2nd core in it.
Since the SCP device node is changed to multi-core structure,
enable SCP cluster to enable probing SCP core 0.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../boot/dts/mediatek/mt8195-cherry.dtsi | 4 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 ++++++++++++++-----
2 files changed, 27 insertions(+), 7 deletions(-)
Comments
Il 10/02/23 09:59, Tinghan Shen ha scritto:
> Rewrite the MT8195 SCP device node as a cluster and
> add the SCP 2nd core in it.
>
> Since the SCP device node is changed to multi-core structure,
> enable SCP cluster to enable probing SCP core 0.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../boot/dts/mediatek/mt8195-cherry.dtsi | 4 +++
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 ++++++++++++++-----
> 2 files changed, 27 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> index 56749cfe7c33..4f9bc7581adb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -933,6 +933,10 @@
> interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> +&scp_cluster {
> + status = "okay";
> +};
> +
> &scp {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 8f1264d5290b..87e49f5fb7b3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -826,14 +826,30 @@
> clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
> };
>
> - scp: scp@10500000 {
> - compatible = "mediatek,mt8195-scp";
> - reg = <0 0x10500000 0 0x100000>,
> - <0 0x10720000 0 0xe0000>,
> - <0 0x10700000 0 0x8000>;
> - reg-names = "sram", "cfg", "l1tcm";
> - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
> + scp_cluster: scp@10500000 {
> + compatible = "mediatek,mt8195-scp-dual";
> + reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>;
> + reg-names = "cfg", "l1tcm";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0x10500000 0x100000>;
> status = "disabled";
> +
> + scp: scp@0 {
Minor nit: Please change this to `scp_c0:`.
Like that, we keep consistency and increase readability, as we're clearly then
reading that one node is for core 0, the other is for core 1.
This is fine even on devices using only a single SCP core, because in devicetree
we are describing the hardware, not the software implemetation of it - and the
MT8195 SoC does, by hardware, have two SCP cores anyway :-)
After which,
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
@@ -933,6 +933,10 @@
interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
};
+&scp_cluster {
+ status = "okay";
+};
+
&scp {
status = "okay";
@@ -826,14 +826,30 @@
clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
};
- scp: scp@10500000 {
- compatible = "mediatek,mt8195-scp";
- reg = <0 0x10500000 0 0x100000>,
- <0 0x10720000 0 0xe0000>,
- <0 0x10700000 0 0x8000>;
- reg-names = "sram", "cfg", "l1tcm";
- interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ scp_cluster: scp@10500000 {
+ compatible = "mediatek,mt8195-scp-dual";
+ reg = <0 0x10720000 0 0xe0000>, <0 0x10700000 0 0x8000>;
+ reg-names = "cfg", "l1tcm";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x10500000 0x100000>;
status = "disabled";
+
+ scp: scp@0 {
+ compatible = "mediatek,scp-core";
+ reg = <0x0 0xa0000>;
+ reg-names = "sram";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
+ scp_c1: scp@a0000 {
+ compatible = "mediatek,scp-core";
+ reg = <0xa0000 0x20000>;
+ reg-names = "sram";
+ interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
};
scp_adsp: clock-controller@10720000 {