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[2620:137:e000::1:20]) by mx.google.com with ESMTP id w8-20020a63a748000000b004fb3c6b3a43si1163073pgo.185.2023.02.08.10.02.27; Wed, 08 Feb 2023 10:02:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JAcWPyMr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231805AbjBHSBF (ORCPT + 99 others); Wed, 8 Feb 2023 13:01:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231645AbjBHSA6 (ORCPT ); Wed, 8 Feb 2023 13:00:58 -0500 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13099530CA for ; Wed, 8 Feb 2023 10:00:54 -0800 (PST) Received: by mail-wm1-x331.google.com with SMTP id bg26so13933742wmb.0 for ; Wed, 08 Feb 2023 10:00:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/2ULfqaWtAXZsjMHKgQGvS+d3WjfdWm7pm2QzT86+1Q=; b=JAcWPyMrT1gIswMyagFQ8OSbzsFQR168lSLRwRMsHBc8jR9PaoOrLOD8dVvifSaoYl qvDJv7JhIjUg4URX6LiyhQLY/6JZt5hNFn4OUnCiBP8yA/r9abJCIhYK4+rBSlyDOyhO OYWxij1CvgaJiMH8E76Q5k3Bf7T36cL+o3KFdc8MycLfAPRjSkDWoWoavY/IUb6xB1SR d/Y41/zi2xLLrBona7QSfMpFmEJsKfclUJBGvF1gETvV4+kVu943dLWqfONQ/2amtBNR eeBFDvFBfIRLFET7OskmjV/BXTIbH6WtYG1um0p1ImUmQFcWSBe9YqDgjOiX9RO1pnns fOxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/2ULfqaWtAXZsjMHKgQGvS+d3WjfdWm7pm2QzT86+1Q=; b=X1xv6R9tF4EAiZdusRRbuLd4aXz68hTWMeQRy4NXQeR820Gb6gG34VzY465nW8gsWm jq9I3QnmIY8/YWwCAWhynbDMcscH/gRlLb4SQYa6YhnFTuypum1WJilQjYSBwrOVPtlS 5k0dFmCHjw8dZjZ4AGHXE4hS+QiVI8/ByWyVRJT8zJJabm9yNH5NT06pzz+U8t1ormGM Te5iY91Z09uZmkK61PKu6GfKUwBuLM9Q1lb2EFjxoL28PbZm98rdF3IBlxGrK3QO5CNc CSv3uEhTokzG8udLML1oXmr6j4cxFzK5csMdriwXCNN91fWXAxaq5oSOtqAM3rBoWD0S ExIA== X-Gm-Message-State: AO0yUKXcCUr/HigJkLL+ry9JquBHpJh4lOr7j+QLKh+ToD7XPWQBHLny ug7YZG6ItHePooTrxKpbQ7OhvA== X-Received: by 2002:a05:600c:19d1:b0:3e0:15b:47b3 with SMTP id u17-20020a05600c19d100b003e0015b47b3mr7486577wmq.32.1675879253472; Wed, 08 Feb 2023 10:00:53 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id k20-20020a05600c169400b003dc54eef495sm2370286wmn.24.2023.02.08.10.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Feb 2023 10:00:52 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Dmitry Baryshkov Subject: [PATCH v9 04/11] phy: qcom-qmp: pcs-pcie: Add v6 register offsets Date: Wed, 8 Feb 2023 20:00:13 +0200 Message-Id: <20230208180020.2761766-5-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230208180020.2761766-1-abel.vesa@linaro.org> References: <20230208180020.2761766-1-abel.vesa@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757286875538089723?= X-GMAIL-MSGID: =?utf-8?q?1757286875538089723?= The new SM8550 SoC bumps up the HW version of QMP phy to v6 for USB, UFS and PCIE g3x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa Reviewed-by: Dmitry Baryshkov --- The v8 of this patch is: https://lore.kernel.org/all/20230206212619.3218741-5-abel.vesa@linaro.org/ Changes since v8: * none Changes since v7: * none Changes since v6: * none Changes since v5: * none Changes since v4: * none Changes since v3: * added Dmitry's R-b tag Changes since v2: * none Changes since v1: * split all the offsets into separate patches, like Vinod suggested drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 0e7aaff2ecfd..05b59f261999 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -29,6 +29,7 @@ #include "phy-qcom-qmp-pcs-pcie-v4_20.h" #include "phy-qcom-qmp-pcs-pcie-v5.h" #include "phy-qcom-qmp-pcs-pcie-v5_20.h" +#include "phy-qcom-qmp-pcs-pcie-v6.h" #include "phy-qcom-qmp-pcie-qhp.h" /* QPHY_SW_RESET bit */ diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h new file mode 100644 index 000000000000..91e70002eb47 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_H_ + +/* Only for QMP V6 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 + +#endif