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Wed, 8 Feb 2023 03:17:30 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 8 Feb 2023 03:17:29 -0800 Received: from mmaddireddy-ubuntu.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Wed, 8 Feb 2023 03:17:23 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , , , , , , , , Manikanta Maddireddy Subject: [RFC,v14 3/5] PCI / PM: Add support for the PCIe WAKE# signal for OF Date: Wed, 8 Feb 2023 16:46:43 +0530 Message-ID: <20230208111645.3863534-4-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230208111645.3863534-1-mmaddireddy@nvidia.com> References: <20230208111645.3863534-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT025:EE_|PH8PR12MB8430:EE_ X-MS-Office365-Filtering-Correlation-Id: 973b9164-0dd2-4938-c10d-08db09c61a8c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Feb 2023 11:17:45.4476 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 973b9164-0dd2-4938-c10d-08db09c61a8c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8430 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757261589510798162?= X-GMAIL-MSGID: =?utf-8?q?1757261589510798162?= From: Jeffy Chen Add of_pci_setup_wake_irq() to parse the PCIe WAKE# interrupt from the device tree and set the wake irq. Add of_pci_teardown_wake_irq() to clear the wake irq. Call of_pci_setup_wake_irq() in pci_device_probe() to setup PCIe WAKE# interrupt during PCIe Endpoint enumeration. Enable or disable PCIe WAKE# interrupt in platform_pci_set_wakeup(). Signed-off-by: Jeffy Chen Signed-off-by: Manikanta Maddireddy --- Changes in v14: pci_platform_pm_ops structure is removed in latest kernel, so dropped pci-of driver. Instead, enable wake in platform_pci_set_wakeup(). Changes in v13: Fix compiler error reported by kbuild test robot Changes in v12: Enable the wake irq in noirq stage to avoid possible irq storm. Changes in v11: Only support 1-per-device PCIe WAKE# pin as suggested. Changes in v10: Use device_set_wakeup_capable() instead of device_set_wakeup_enable(), since dedicated wakeirq will be lost in device_set_wakeup_enable(false). Changes in v9: Fix check error in .cleanup(). Move dedicated wakeirq setup to setup() callback and use device_set_wakeup_enable() to enable/disable. Changes in v8: Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal. Changes in v7: Move PCIE_WAKE handling into pci core. Changes in v6: Fix device_init_wake error handling, and add some comments. Changes in v5: Rebase. Changes in v3: Fix error handling. Changes in v2: Use dev_pm_set_dedicated_wake_irq. drivers/pci/of.c | 49 ++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci-driver.c | 10 ++++++++ drivers/pci/pci.c | 7 ++++++ drivers/pci/pci.h | 8 +++++++ 4 files changed, 74 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index ff897c40ed71..1c348e63f175 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "pci.h" #ifdef CONFIG_PCI @@ -705,3 +706,51 @@ u32 of_pci_get_slot_power_limit(struct device_node *node, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + struct pci_dev *ppdev; + struct device_node *dn; + int ret, irq; + + /* Get the pci_dev of our parent. Hopefully it's a port. */ + ppdev = pdev->bus->self; + /* Nope, it's a host bridge. */ + if (!ppdev) + return 0; + + dn = pci_device_to_OF_node(ppdev); + if (!dn) + return 0; + + irq = of_irq_get_byname(dn, "wakeup"); + if (irq == -EPROBE_DEFER) { + return irq; + } else if (irq < 0) { + /* Ignore other errors, since a missing wakeup is non-fatal. */ + dev_info(&pdev->dev, "cannot get wakeup interrupt: %d\n", irq); + return 0; + } + + device_init_wakeup(&pdev->dev, true); + + ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, irq); + if (ret < 0) { + dev_err(&pdev->dev, "failed to set wake IRQ: %d\n", ret); + device_init_wakeup(&pdev->dev, false); + return ret; + } + + /* Start out disabled to avoid irq storm */ + dev_pm_disable_wake_irq(&pdev->dev); + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_setup_wake_irq); + +void of_pci_teardown_wake_irq(struct pci_dev *pdev) +{ + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); +} +EXPORT_SYMBOL_GPL(of_pci_teardown_wake_irq); diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index d934c27491c4..fca966137fac 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -456,10 +457,17 @@ static int pci_device_probe(struct device *dev) if (error < 0) return error; + error = of_pci_setup_wake_irq(pci_dev); + if (error < 0) { + pcibios_free_irq(pci_dev); + return error; + } + pci_dev_get(pci_dev); error = __pci_device_probe(drv, pci_dev); if (error) { pcibios_free_irq(pci_dev); + of_pci_teardown_wake_irq(pci_dev); pci_dev_put(pci_dev); } @@ -471,6 +479,8 @@ static void pci_device_remove(struct device *dev) struct pci_dev *pci_dev = to_pci_dev(dev); struct pci_driver *drv = pci_dev->driver; + of_pci_teardown_wake_irq(pci_dev); + if (drv->remove) { pm_runtime_get_sync(dev); drv->remove(pci_dev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fba95486caaf..332a0b98b6c3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -1052,6 +1053,12 @@ static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) if (pci_use_mid_pm()) return PCI_POWER_ERROR; + /* Enable or disable wakeirq if set via device tree. */ + if (enable) + dev_pm_enable_wake_irq(&dev->dev); + else + dev_pm_disable_wake_irq(&dev->dev); + return acpi_pci_wakeup(dev, enable); } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 9ed3b5550043..83a2af148631 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -631,6 +631,8 @@ int of_pci_get_max_link_speed(struct device_node *node); u32 of_pci_get_slot_power_limit(struct device_node *node, u8 *slot_power_limit_value, u8 *slot_power_limit_scale); +int of_pci_setup_wake_irq(struct pci_dev *pdev); +void of_pci_teardown_wake_irq(struct pci_dev *pdev); void pci_set_of_node(struct pci_dev *dev); void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); @@ -669,6 +671,12 @@ of_pci_get_slot_power_limit(struct device_node *node, return 0; } +static inline int of_pci_setup_wake_irq(struct pci_dev *pdev) +{ + return 0; +} + +static inline void of_pci_teardown_wake_irq(struct pci_dev *pdev) { } static inline void pci_set_of_node(struct pci_dev *dev) { } static inline void pci_release_of_node(struct pci_dev *dev) { } static inline void pci_set_bus_of_node(struct pci_bus *bus) { }