diff mbox series

[RFC,v14,1/5] dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq

Message ID 20230208111645.3863534-2-mmaddireddy@nvidia.com
State New
Headers
Series Add DT based PCIe wake support in PCI core driver |

Commit Message

Manikanta Maddireddy Feb. 8, 2023, 11:16 a.m. UTC 
  From: Jeffy Chen <jeffy.chen@rock-chips.com>

Add device tree support to pass PCIe WAKE# pin information to PCI core
driver. To support PCIe WAKE# and PCI irqs, add definition of the optional
properties "interrupts" and "interrupt-names". These properties should be
defined by the PCIe port to which wake capable Endpoint is connected,
so the definition is added under "PCI-PCI Bridge properties" section.

Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---

Changes in v14:
Move the device tree properties definition to "PCI-PCI Bridge properties"
section and also update commit message.

Changes in v13: None
Changes in v12:
Only add irq definitions for PCI devices and rewrite the commit message.

Changes in v11: None
Changes in v10: None
Changes in v9:
Add section for PCI devices and rewrite the commit message.

Changes in v8:
Add optional "pci", and rewrite commit message.

Changes in v7: None
Changes in v6: None
Changes in v5:
Move to pci.txt

Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/pci/pci.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Rob Herring Feb. 8, 2023, 1:53 p.m. UTC | #1 
On Wed, Feb 8, 2023 at 5:17 AM Manikanta Maddireddy
<mmaddireddy@nvidia.com> wrote:
>
> From: Jeffy Chen <jeffy.chen@rock-chips.com>
>
> Add device tree support to pass PCIe WAKE# pin information to PCI core
> driver. To support PCIe WAKE# and PCI irqs, add definition of the optional
> properties "interrupts" and "interrupt-names". These properties should be
> defined by the PCIe port to which wake capable Endpoint is connected,
> so the definition is added under "PCI-PCI Bridge properties" section.
>
> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> Reviewed-by: Rob Herring <robh@kernel.org>

I did? 5 years ago it seems. Times change and evolve. Don't add to
pci.txt. This must be a schema now. PCI schema lives in dtschema.

Rob
Manikanta Maddireddy Feb. 8, 2023, 3:54 p.m. UTC | #2 
On 2/8/2023 7:23 PM, Rob Herring wrote:
> External email: Use caution opening links or attachments
>
>
> On Wed, Feb 8, 2023 at 5:17 AM Manikanta Maddireddy
> <mmaddireddy@nvidia.com> wrote:
>> From: Jeffy Chen <jeffy.chen@rock-chips.com>
>>
>> Add device tree support to pass PCIe WAKE# pin information to PCI core
>> driver. To support PCIe WAKE# and PCI irqs, add definition of the optional
>> properties "interrupts" and "interrupt-names". These properties should be
>> defined by the PCIe port to which wake capable Endpoint is connected,
>> so the definition is added under "PCI-PCI Bridge properties" section.
>>
>> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
> I did? 5 years ago it seems. Times change and evolve. Don't add to
> pci.txt. This must be a schema now. PCI schema lives in dtschema.
>
> Rob
I will prepare new patch in dtschema and send in next version.

Manikanta
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 6a8f2874a24d..53bd559a7305 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -71,6 +71,14 @@  Optional properties:
    trusted with relaxed DMA protection, as users could easily attach
    malicious devices to this port.
 
+- interrupts: Interrupt specifier for each name in interrupt-names.
+- interrupt-names:
+    May contain "wakeup" for PCIe WAKE# interrupt and "pci" for PCI interrupt.
+    The PCI devices may optionally include an 'interrupts' property that
+    represents the legacy PCI interrupt. And when we try to specify the PCIe
+    WAKE# pin, a corresponding 'interrupt-names' property is required to
+    distinguish them.
+
 Example:
 
 pcie@10000000 {