diff mbox series

[v1,13/45] clk: mediatek: mt8167: Compress GATE_TOPx macros

Message ID	20230206152928.918562-14-angelogioacchino.delregno@collabora.com
State	New
Headers	Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 508506602F93; Mon, 6 Feb 2023 15:30:03 +0000 (GMT) From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, daniel@makrotopia.org, fparent@baylibre.com, msp@baylibre.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, zhaojh329@gmail.com, sam.shih@mediatek.com, edward-jw.yang@mediatek.com, yangyingliang@huawei.com, granquet@baylibre.com, pablo.sun@mediatek.com, sean.wang@mediatek.com, chen.zhong@mediatek.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v1 13/45] clk: mediatek: mt8167: Compress GATE_TOPx macros Date: Mon, 6 Feb 2023 16:28:56 +0100 Message-Id: <20230206152928.918562-14-angelogioacchino.delregno@collabora.com> In-Reply-To: <20230206152928.918562-1-angelogioacchino.delregno@collabora.com> References: <20230206152928.918562-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	MediaTek clocks: full module build and cleanups \| [v1,00/45] MediaTek clocks: full module build and cleanups [v1,01/45] clk: mediatek: clk-mtk: Switch to device_get_match_data() [v1,02/45] clk: mediatek: clk-mtk: Introduce clk_mtk_pdev_{probe,remove}() [v1,03/45] clk: mediatek: Migrate to mtk_clk_pdev_probe() for multimedia clocks [v1,04/45] clk: mediatek: Add divider clocks to mtk_clk_simple_{probe,remove}() [v1,05/45] clk: mediatek: mt2712: Migrate topckgen/mcucfg to mtk_clk_simple_probe() [v1,06/45] clk: mediatek: mt2712: Compress clock arrays entries to 90 columns [v1,07/45] clk: mediatek: mt2712: Add error handling to clk_mt2712_apmixed_probe() [v1,08/45] clk: mediatek: mt2712: Move apmixedsys clock driver to its own file [v1,09/45] clk: mediatek: mt2712: Change to use module_platform_driver macro [v1,10/45] clk: mediatek: mt2712: Change Kconfig options to allow module build [v1,11/45] clk: mediatek: mt8365: Move apmixedsys clock driver to its own file [v1,12/45] clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}() [v1,13/45] clk: mediatek: mt8167: Compress GATE_TOPx macros [v1,14/45] clk: mediatek: mt8167: Move apmixedsys as platform_driver in new file [v1,15/45] clk: mediatek: mt8167: Remove __initconst annotation from arrays [v1,16/45] clk: mediatek: mt8167: Convert to mtk_clk_simple_{probe,remove}() [v1,17/45] clk: mediatek: mt8183: Move apmixedsys clock driver to its own file [v1,18/45] clk: mediatek: mt8183: Compress clocks arrays entries where possible [v1,19/45] clk: mediatek: mt8183: Convert all remaining clocks to common probe [v1,20/45] clk: mediatek: Consistently use GATE_MTK() macro [v1,21/45] clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag [v1,22/45] clk: mediatek: mt7622: Move apmixedsys clock driver to its own file [v1,23/45] clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c [v1,24/45] clk: mediatek: mt7622: Convert to platform driver and simple probe [v1,25/45] clk: mediatek: mt8516: Move apmixedsys clock driver to its own file [v1,26/45] clk: mediatek: mt8516: Convert to platform driver and simple probe [v1,27/45] clk: mediatek: mt8516: Allow building clock drivers as modules [v1,28/45] clk: mediatek: Propagate struct device with mtk_clk_register_dividers() [v1,29/45] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set critical clock [v1,30/45] clk: mediatek: mt7986-infracfg: Migrate to common probe mechanism [v1,31/45] clk: mediatek: mt7986-eth: Migrate to common probe mechanism [v1,32/45] clk: mediatek: mt8186-mcu: Migrate to common probe mechanism [v1,33/45] clk: mediatek: Switch to module_platform_driver() where possible [v1,34/45] clk: mediatek: Add MODULE_LICENSE() where missing [v1,35/45] clk: mediatek: Split MT8195 clock drivers and allow module build [v1,36/45] clk: mediatek: Allow building MT8192 non-critical clocks as modules [v1,37/45] clk: mediatek: Allow MT7622 clocks to be built as modules [v1,38/45] clk: mediatek: Allow all MT8167 clocks to be built as modules [v1,39/45] clk: mediatek: Allow all MT8183 clocks to be built as modules [v1,40/45] clk: mediatek: Allow building most MT6765 clock drivers as modules [v1,41/45] clk: mediatek: Allow building most MT6797 clock drivers as modules [v1,42/45] clk: mediatek: Split configuration options for MT8186 clock drivers [v1,43/45] clk: mediatek: mt8192: Move apmixedsys clock driver to its own file [v1,44/45] clk: mediatek: Kconfig: Allow module build for core mt8192 clocks [v1,45/45] clk: mediatek: Add MODULE_DEVICE_TABLE() where appropriate

Commit Message

AngeloGioacchino Del Regno Feb. 6, 2023, 3:28 p.m. UTC

  Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
No functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mt8167.c | 88 +++++++++----------------------
 1 file changed, 24 insertions(+), 64 deletions(-)

Comments

Chen-Yu Tsai Feb. 7, 2023, 7:30 a.m. UTC | #1

On Mon, Feb 6, 2023 at 11:30 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
> No functional changes.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/clk/mediatek/clk-mt8167.c | 88 +++++++++----------------------
>  1 file changed, 24 insertions(+), 64 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c
> index 91669ebafaf9..97a443fdfc77 100644
> --- a/drivers/clk/mediatek/clk-mt8167.c
> +++ b/drivers/clk/mediatek/clk-mt8167.c
> @@ -736,77 +736,37 @@ static const struct mtk_gate_regs top5_cg_regs = {
>         .sta_ofs = 0x44,
>  };
>
> -#define GATE_TOP0(_id, _name, _parent, _shift) {       \
> -               .id = _id,                              \
> -               .name = _name,                          \
> -               .parent_name = _parent,                 \
> -               .regs = &top0_cg_regs,                  \
> -               .shift = _shift,                        \
> -               .ops = &mtk_clk_gate_ops_setclr,        \
> -       }
> +#define GATE_TOP0(_id, _name, _parent, _shift)                 \
> +       GATE_MTK(_id, _name, _parent, &top0_cg_regs,            \
> +                _shift, &mtk_clk_gate_ops_setclr)

Nit: 100 characters should be enough to fit the whole GATE_MTK part in one
line.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

AngeloGioacchino Del Regno Feb. 7, 2023, 9:17 a.m. UTC | #2

Il 07/02/23 08:30, Chen-Yu Tsai ha scritto:
> On Mon, Feb 6, 2023 at 11:30 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
>> No functional changes.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/clk/mediatek/clk-mt8167.c | 88 +++++++++----------------------
>>   1 file changed, 24 insertions(+), 64 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c
>> index 91669ebafaf9..97a443fdfc77 100644
>> --- a/drivers/clk/mediatek/clk-mt8167.c
>> +++ b/drivers/clk/mediatek/clk-mt8167.c
>> @@ -736,77 +736,37 @@ static const struct mtk_gate_regs top5_cg_regs = {
>>          .sta_ofs = 0x44,
>>   };
>>
>> -#define GATE_TOP0(_id, _name, _parent, _shift) {       \
>> -               .id = _id,                              \
>> -               .name = _name,                          \
>> -               .parent_name = _parent,                 \
>> -               .regs = &top0_cg_regs,                  \
>> -               .shift = _shift,                        \
>> -               .ops = &mtk_clk_gate_ops_setclr,        \
>> -       }
>> +#define GATE_TOP0(_id, _name, _parent, _shift)                 \
>> +       GATE_MTK(_id, _name, _parent, &top0_cg_regs,            \
>> +                _shift, &mtk_clk_gate_ops_setclr)
> 
> Nit: 100 characters should be enough to fit the whole GATE_MTK part in one
> line.
> 

Wanted to stay below 90, but there's effectively no real reason to do that,
so let's go to 100 cols!

> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>


Cheers,
Angelo

diff mbox series

Patch

diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c
index 91669ebafaf9..97a443fdfc77 100644
--- a/drivers/clk/mediatek/clk-mt8167.c
+++ b/drivers/clk/mediatek/clk-mt8167.c
@@ -736,77 +736,37 @@  static const struct mtk_gate_regs top5_cg_regs = {
 	.sta_ofs = 0x44,
 };
 
-#define GATE_TOP0(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP0(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top0_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP0_I(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top0_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-	}
+#define GATE_TOP0_I(_id, _name, _parent, _shift)		\
+	GATE_MTK(_id, _name, _parent, &top0_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr_inv)
 
-#define GATE_TOP1(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top1_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP1(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top1_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP2(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top2_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP2(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top2_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP2_I(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top2_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-	}
+#define GATE_TOP2_I(_id, _name, _parent, _shift)		\
+	GATE_MTK(_id, _name, _parent, &top2_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr_inv)
 
-#define GATE_TOP3(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top3_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr,	\
-	}
+#define GATE_TOP3(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top3_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr)
 
-#define GATE_TOP4_I(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top4_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_setclr_inv,	\
-	}
+#define GATE_TOP4_I(_id, _name, _parent, _shift)		\
+	GATE_MTK(_id, _name, _parent, &top4_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_setclr_inv)
 
-#define GATE_TOP5(_id, _name, _parent, _shift) {	\
-		.id = _id,				\
-		.name = _name,				\
-		.parent_name = _parent,			\
-		.regs = &top5_cg_regs,			\
-		.shift = _shift,			\
-		.ops = &mtk_clk_gate_ops_no_setclr,	\
-	}
+#define GATE_TOP5(_id, _name, _parent, _shift)			\
+	GATE_MTK(_id, _name, _parent, &top5_cg_regs,		\
+		 _shift, &mtk_clk_gate_ops_no_setclr)
 
 static const struct mtk_gate top_clks[] __initconst = {
 	/* TOP0 */