From patchwork Mon Feb 6 06:33:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Huang, Ying" X-Patchwork-Id: 53020 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2082467wrn; Sun, 5 Feb 2023 22:37:36 -0800 (PST) X-Google-Smtp-Source: AK7set+4TvBUj7DWDEYMgu8PpfKKhOEQG+yfI+xReMfKo6QGYLkPIyBjXCw/jAVwxITgUJtR6k78 X-Received: by 2002:a05:6a20:3944:b0:bf:bcfb:1fc6 with SMTP id r4-20020a056a20394400b000bfbcfb1fc6mr16696744pzg.60.1675665455788; Sun, 05 Feb 2023 22:37:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675665455; cv=none; d=google.com; s=arc-20160816; b=pzFVkZEOE7Qg1t7WeSx4s6bMH4VS77IVJTaGYZBgu+/UiSlUjSpgH/BgQp5hmtNcsq H0edS7dKyWWeDxhTVMvzTWkCrfm+ME3jEQGEOtLCFAFj6TYYYc/DqaS5SNO07bGVKAWh q00pxEjyqcB/oRRYzZM1qm0rH/wfGRuIx0vVYOGxAvfLUlHi2Nf03lYxtErQbKpyUKLp cNRpOI2e+vOOu4+CnSu6HTOyc0mRSaW/oiiEL2xvD9FsYNORJIsBAgOA5yTaeE7VZOHP KhjmL6E4ilSwGPThrybXn9Tg8Yb5JrORW6gtiB6tiI+d29FN1ISlbIUaKCb895RVp+GH /c5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UH9aUpK4brvbUaQ61RpzxwNgcTTe1J3JqNYarO9pDJg=; b=zAh2WnOIWoZUmYduUsMHEbeE/BTeO1dpZxnPJ2v2I251Uwssba3pAD9n8kmDoVOgs3 BOF0+8iKHVCxnzAMXr1rRox24+6B71pqbYGo7DRJA8qtvBcYvFuRY6Upeg0BoIglfuDl UEuxebNcxgwahfglg6R5kfFSBI9rC8hAq1xTLmR2mALFzeJ1KKeHFdGmv0AYeMlWvv5G MRsff0iMPfm82QqMzpy2OQCzmTAKOH81m/7ydGVc5uB/GpioGE4YDa+fdJgt42V2NKCJ ZntkZ6zm9QDJvQy3TWrbmdtTfL2SRVSaD4GHA7byz2R+Nf3wYNi52xa6LhUlV2QoyFWq Uc/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="LPuxEb2/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v185-20020a6389c2000000b004f1a86fee0esi12134798pgd.399.2023.02.05.22.37.23; Sun, 05 Feb 2023 22:37:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="LPuxEb2/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229735AbjBFGes (ORCPT + 99 others); Mon, 6 Feb 2023 01:34:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229692AbjBFGeb (ORCPT ); Mon, 6 Feb 2023 01:34:31 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12FCA1CACC for ; Sun, 5 Feb 2023 22:34:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675665252; x=1707201252; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b/06ZIkmccm+2w2sDb3OOn+m3OxExo5G5C0UlpBP/5Y=; b=LPuxEb2/IY2BiidQxbkk/x4Y0W8CYm3ypm/2UV3W8dXpokTLZN8PMdGq MndPJ3YTH/NpT/3X2D9VhJA1h6Uc1cQKiCoz7tMk6f32TLm88fw1Fp4vD cqSk0tbyKJW9LpYK8EaTHNNeSaP96FUO2NghTCN5na1UBadnWMcEvwxsH wRpfZATDxUQf3kbFDB+1bKl515tI/qOVHVz9/8mlp0DDKflwjULz4E0ES GvKO815td/4gZSREtRmh3cbOile7utL8NcJu3fvg18q2b7sTydT4tssC3 /URX1pXtduvfsCj+EMK/bC7f2Uiu+bMNR6ZQ3ch8B4ZFnBrTRKVaIxvlI w==; X-IronPort-AV: E=McAfee;i="6500,9779,10612"; a="330432771" X-IronPort-AV: E=Sophos;i="5.97,276,1669104000"; d="scan'208";a="330432771" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2023 22:34:11 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10612"; a="659744793" X-IronPort-AV: E=Sophos;i="5.97,276,1669104000"; d="scan'208";a="659744793" Received: from baoyumen-mobl.ccr.corp.intel.com (HELO yhuang6-mobl2.smartont.net) ([10.255.30.227]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2023 22:34:05 -0800 From: Huang Ying To: Andrew Morton Cc: linux-mm@kvack.org, linux-kernel@vger.kernel.org, Huang Ying , Zi Yan , Yang Shi , Baolin Wang , Oscar Salvador , Matthew Wilcox , Bharata B Rao , Alistair Popple , haoxin , Minchan Kim , Mike Kravetz , Hyeonggon Yoo <42.hyeyoo@gmail.com> Subject: [PATCH -v4 8/9] migrate_pages: batch flushing TLB Date: Mon, 6 Feb 2023 14:33:12 +0800 Message-Id: <20230206063313.635011-9-ying.huang@intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230206063313.635011-1-ying.huang@intel.com> References: <20230206063313.635011-1-ying.huang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1757062581134144863?= X-GMAIL-MSGID: =?utf-8?q?1757062581134144863?= The TLB flushing will cost quite some CPU cycles during the folio migration in some situations. For example, when migrate a folio of a process with multiple active threads that run on multiple CPUs. After batching the _unmap and _move in migrate_pages(), the TLB flushing can be batched easily with the existing TLB flush batching mechanism. This patch implements that. We use the following test case to test the patch. On a 2-socket Intel server, - Run pmbench memory accessing benchmark - Run `migratepages` to migrate pages of pmbench between node 0 and node 1 back and forth. With the patch, the TLB flushing IPI reduces 99.1% during the test and the number of pages migrated successfully per second increases 291.7%. NOTE: TLB flushing is batched only for normal folios, not for THP folios. Because the overhead of TLB flushing for THP folios is much lower than that for normal folios (about 1/512 on x86 platform). Signed-off-by: "Huang, Ying" Cc: Zi Yan Cc: Yang Shi Cc: Baolin Wang Cc: Oscar Salvador Cc: Matthew Wilcox Cc: Bharata B Rao Cc: Alistair Popple Cc: haoxin Cc: Minchan Kim Cc: Mike Kravetz Cc: Hyeonggon Yoo <42.hyeyoo@gmail.com> --- mm/migrate.c | 4 +++- mm/rmap.c | 20 +++++++++++++++++--- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/mm/migrate.c b/mm/migrate.c index 9378fa2ad4a5..ca6e2ff02a09 100644 --- a/mm/migrate.c +++ b/mm/migrate.c @@ -1230,7 +1230,7 @@ static int migrate_folio_unmap(new_page_t get_new_page, free_page_t put_new_page /* Establish migration ptes */ VM_BUG_ON_FOLIO(folio_test_anon(src) && !folio_test_ksm(src) && !anon_vma, src); - try_to_migrate(src, 0); + try_to_migrate(src, TTU_BATCH_FLUSH); page_was_mapped = 1; } @@ -1781,6 +1781,8 @@ static int migrate_pages_batch(struct list_head *from, new_page_t get_new_page, stats->nr_thp_failed += thp_retry; stats->nr_failed_pages += nr_retry_pages; move: + try_to_unmap_flush(); + retry = 1; for (pass = 0; pass < NR_MAX_MIGRATE_PAGES_RETRY && (retry || large_retry); diff --git a/mm/rmap.c b/mm/rmap.c index b616870a09be..2e125f3e462e 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -1976,7 +1976,21 @@ static bool try_to_migrate_one(struct folio *folio, struct vm_area_struct *vma, } else { flush_cache_page(vma, address, pte_pfn(*pvmw.pte)); /* Nuke the page table entry. */ - pteval = ptep_clear_flush(vma, address, pvmw.pte); + if (should_defer_flush(mm, flags)) { + /* + * We clear the PTE but do not flush so potentially + * a remote CPU could still be writing to the folio. + * If the entry was previously clean then the + * architecture must guarantee that a clear->dirty + * transition on a cached TLB entry is written through + * and traps if the PTE is unmapped. + */ + pteval = ptep_get_and_clear(mm, address, pvmw.pte); + + set_tlb_ubc_flush_pending(mm, pte_dirty(pteval)); + } else { + pteval = ptep_clear_flush(vma, address, pvmw.pte); + } } /* Set the dirty flag on the folio now the pte is gone. */ @@ -2148,10 +2162,10 @@ void try_to_migrate(struct folio *folio, enum ttu_flags flags) /* * Migration always ignores mlock and only supports TTU_RMAP_LOCKED and - * TTU_SPLIT_HUGE_PMD and TTU_SYNC flags. + * TTU_SPLIT_HUGE_PMD, TTU_SYNC, and TTU_BATCH_FLUSH flags. */ if (WARN_ON_ONCE(flags & ~(TTU_RMAP_LOCKED | TTU_SPLIT_HUGE_PMD | - TTU_SYNC))) + TTU_SYNC | TTU_BATCH_FLUSH))) return; if (folio_is_zone_device(folio) &&