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[2620:137:e000::1:20]) by mx.google.com with ESMTP id vf8-20020a170907238800b0087880aa5e39si162117ejb.505.2023.02.03.09.09.08; Fri, 03 Feb 2023 09:09:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=pZjQluKZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233592AbjBCQ5I (ORCPT + 99 others); Fri, 3 Feb 2023 11:57:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233698AbjBCQ4u (ORCPT ); Fri, 3 Feb 2023 11:56:50 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10F5BAA241; Fri, 3 Feb 2023 08:56:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1675443403; x=1706979403; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6kdLwMzgKaekoqREZO4N3DxdvJmgI6d16KmZssVRLe8=; b=pZjQluKZM3hDrxfKB5SgagxtTB7WFgG83d1kZIpvd5InLj40v8yS89GB Pwl06TQ6LG22c2OrK7pqgPmOI0HL/DreFT/7rJ93DupIM3VMKC5L61eP6 wMrd0AEKuosim+f19+BmoAn2ky6hKQ4wi59IDG+SHyzqxyGe1ha1r0Zgp Y+LVcdvaXbL8hnHTpASs6uIl7bdai7ACf2JaZf+bMUfG9quD/kXKVeUoQ FND/4FzFVLimQOWyhT4pugklKuGJqJOLy+i3WBD9G8CZx41T6fZVYrevE F4m3nCr0SwQe0SDH0JTOreL1UyGHhhLjbwZt9hqkIQE2zx1z22/obzN8B A==; X-IronPort-AV: E=Sophos;i="5.97,271,1669100400"; d="scan'208";a="198833370" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Feb 2023 09:56:42 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Fri, 3 Feb 2023 09:56:40 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.16 via Frontend Transport; Fri, 3 Feb 2023 09:56:34 -0700 From: Kumaravel Thiagarajan To: CC: , , , , , , , , , , , , , , , , Tharun Kumar P Subject: [PATCH v11 tty-next 3/4] serial: 8250_pci1xxxx: Add RS485 support to quad-uart driver Date: Sat, 4 Feb 2023 11:01:37 +0530 Message-ID: <20230204053138.2520105-4-kumaravel.thiagarajan@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230204053138.2520105-1-kumaravel.thiagarajan@microchip.com> References: <20230204053138.2520105-1-kumaravel.thiagarajan@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DATE_IN_FUTURE_12_24, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756830548301402247?= X-GMAIL-MSGID: =?utf-8?q?1756830548301402247?= pci1xxxx uart supports RS485 mode of operation in the hardware with auto-direction control with configurable delay for releasing RTS after the transmission. This patch adds support for the RS485 mode. Co-developed-by: Tharun Kumar P Signed-off-by: Tharun Kumar P Signed-off-by: Kumaravel Thiagarajan Reviewed-by: Ilpo Järvinen --- Changes in v11: - No Change Changes in v10: - No Change Changes in v9: - No Change Changes in v8: - Modified datatype of delay_in_baud_periods to u32 Changes in v7: - No Change Changes in v6: - Modified datatype of delay_in_baud_periods to u64 to avoid overflows Changes in v5: - Removed unnecessary assignments - Corrected styling issues in comments Changes in v4: - No Change Changes in v3: - Remove flags sanitization in driver which is taken care in core Changes in v2: - move pci1xxxx_rs485_config to a separate patch with pci1xxxx_rs485_supported. --- drivers/tty/serial/8250/8250_pci1xxxx.c | 50 +++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci1xxxx.c b/drivers/tty/serial/8250/8250_pci1xxxx.c index ea04c014edb9..58f47d18f7d8 100644 --- a/drivers/tty/serial/8250/8250_pci1xxxx.c +++ b/drivers/tty/serial/8250/8250_pci1xxxx.c @@ -164,6 +164,54 @@ static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud, port->membase + UART_BAUD_CLK_DIVISOR_REG); } +static int pci1xxxx_rs485_config(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u32 delay_in_baud_periods; + u32 baud_period_in_ns; + u32 mode_cfg = 0; + u32 clock_div; + + /* + * pci1xxxx's uart hardware supports only RTS delay after + * Tx and in units of bit times to a maximum of 15 + */ + if (rs485->flags & SER_RS485_ENABLED) { + mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL; + + if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) + mode_cfg |= ADCL_CFG_POL_SEL; + + if (rs485->delay_rts_after_send) { + clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); + baud_period_in_ns = + FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) * + UART_BIT_SAMPLE_CNT; + delay_in_baud_periods = + rs485->delay_rts_after_send * NSEC_PER_MSEC / + baud_period_in_ns; + delay_in_baud_periods = + min_t(u32, delay_in_baud_periods, + FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK)); + mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK, + delay_in_baud_periods); + rs485->delay_rts_after_send = + baud_period_in_ns * delay_in_baud_periods / + NSEC_PER_MSEC; + } + } + writel(mode_cfg, port->membase + ADCL_CFG_REG); + return 0; +} + +static const struct serial_rs485 pci1xxxx_rs485_supported = { + .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND, + .delay_rts_after_send = 1, + /* Delay RTS before send is not supported */ +}; + static int pci1xxxx_setup(struct pci_dev *pdev, struct uart_8250_port *port, int port_idx) { @@ -174,6 +222,8 @@ static int pci1xxxx_setup(struct pci_dev *pdev, port->port.set_termios = serial8250_do_set_termios; port->port.get_divisor = pci1xxxx_get_divisor; port->port.set_divisor = pci1xxxx_set_divisor; + port->port.rs485_config = pci1xxxx_rs485_config; + port->port.rs485_supported = pci1xxxx_rs485_supported; ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0); if (ret < 0)