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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i25-20020a0564020f1900b0049e37585a7bsi2074014eda.196.2023.02.03.00.21.33; Fri, 03 Feb 2023 00:21:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P5XaQfQB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232869AbjBCITn (ORCPT + 99 others); Fri, 3 Feb 2023 03:19:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232600AbjBCITH (ORCPT ); Fri, 3 Feb 2023 03:19:07 -0500 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31B326CCAA for ; Fri, 3 Feb 2023 00:18:31 -0800 (PST) Received: by mail-wm1-x329.google.com with SMTP id o36so3250980wms.1 for ; Fri, 03 Feb 2023 00:18:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gVGVV9qGjZMfe1gxAo5nZfKax+1XIxmkt82fjMeK7iM=; b=P5XaQfQBAwl14ujPzil4GdTDK6ey401OHEEOGYffQJraDbJKABSVD7g1VFeQvCAqVe MkQAbn9azYKRwkO6mJLuz2hKI7fooL2j08rjSdn+/BQByFiDR+ZUeoCHj4mqnYTHlp2g n9TAF3xrUPgeFehRYnQiSCMI+hjvMxi/Q2/SJV5ye6X7rusrC2oUlHcKRBpPI0ayWov+ xgbiShkaGXrc2EMhTWSmLBaodDSsiKkrIDqic/DRrzVwTB/dE1ao3Kz/LeZ6k9PKsjwb NlQfZtqhHibupfyDILF7Wt+KpfziP7amnUdQW/nTea66Pyq6AtQbEvPO0AfyRpklg1hl wOFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gVGVV9qGjZMfe1gxAo5nZfKax+1XIxmkt82fjMeK7iM=; b=cduCeGFrTFdX4CxnRNAYX5PnO4kpDLLxarcHx9AWLORugyaItjjd22lIkk5n4bAk/f 6i5dyIncyRvg9AcdIIg8nfjTpcK+GoSsvMYiRdP8YrgQhqQmStPu2bxwpFFoHbRE2YrY zeuFHmFL1dfPODlyEltGO9tVaY0kGNa7TGL3kVVeaY39v/G4jFibHL/dHk7B+W5sibii dkVspBiqtvP7NMYdI1Z8tqhH7Mf1Jb4xMFIo+FqlRZaw1zgkW4MpAW8ExBEB0bKU5Bzy qGf2ao+0fetCkK0Zk+hFVKiPF1wjFaEYhGjiYqqpzngAe6dYPr61Dwd61MZuMNcZJlaI 4URA== X-Gm-Message-State: AO0yUKUnMcR+tHjAfMpJlDI8L5lOeAV7nDLq44Lp7cut6SWqjDZEDuEp GQnKPBZPLgqeJpmIAsPC24Glaw== X-Received: by 2002:a05:600c:3553:b0:3df:578c:50d4 with SMTP id i19-20020a05600c355300b003df578c50d4mr6945705wmq.21.1675412310660; Fri, 03 Feb 2023 00:18:30 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id az24-20020a05600c601800b003dc4baaedd3sm7316591wmb.37.2023.02.03.00.18.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Feb 2023 00:18:30 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , Neil Armstrong Subject: [PATCH v7 12/12] arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodes Date: Fri, 3 Feb 2023 10:18:07 +0200 Message-Id: <20230203081807.2248625-13-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230203081807.2248625-1-abel.vesa@linaro.org> References: <20230203081807.2248625-1-abel.vesa@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756797355668723903?= X-GMAIL-MSGID: =?utf-8?q?1756797355668723903?= Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa --- This patch does not have a v3, but since it is now part of the same patchset with the controller and the phy drivers patches, I had to bump the version to 4. The v6 was here: https://lore.kernel.org/all/20230202123902.3831491-13-abel.vesa@linaro.org/ Changes since v6: * none Changes since v5: * none Changes since v4: * moved here the pinctrl properties and out of dtsi file Changes since v2: * none Changes since v1: * ordered pcie related nodes alphabetically in MTP dts * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes * dropped the child node from the phy nodes, like Johan suggested, and updated to use the sc8280xp binding scheme * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy to "nocsr" * reordered all pcie nodes properties to look similar to the ones from sc8280xp arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index e756f83a941c..265862d0e44f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -407,6 +407,44 @@ &mdss_mdp { status = "okay"; }; +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12";