Message ID | 20230203081807.2248625-13-abel.vesa@linaro.org |
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State | New |
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sm8550: Add PCIe HC and PHY support
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Commit Message
Abel Vesa
Feb. 3, 2023, 8:18 a.m. UTC
Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- This patch does not have a v3, but since it is now part of the same patchset with the controller and the phy drivers patches, I had to bump the version to 4. The v6 was here: https://lore.kernel.org/all/20230202123902.3831491-13-abel.vesa@linaro.org/ Changes since v6: * none Changes since v5: * none Changes since v4: * moved here the pinctrl properties and out of dtsi file Changes since v2: * none Changes since v1: * ordered pcie related nodes alphabetically in MTP dts * dropped the pipe_mux, phy_pipe and ref clocks from the pcie nodes * dropped the child node from the phy nodes, like Johan suggested, and updated to use the sc8280xp binding scheme * changed "pcie_1_nocsr_com_phy_reset" 2nd reset name of pcie1_phy to "nocsr" * reordered all pcie nodes properties to look similar to the ones from sc8280xp arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
Comments
On Fri, Feb 03, 2023 at 10:18:07AM +0200, Abel Vesa wrote: > Enable PCIe controllers and PHYs nodes on SM8550 MTP board. > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > +&pcie_1_phy_aux_clk { > + clock-frequency = <1000>; > +}; > + > +&pcie0 { > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie0_default_state>; > + > + status = "okay"; > +}; > + > +&pcie0_phy { > + vdda-phy-supply = <&vreg_l1e_0p88>; > + vdda-pll-supply = <&vreg_l3e_1p2>; Super nit: add newline for consistency. > + status = "okay"; > +}; > + > +&pcie1 { > + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; > + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; Neither controller needs the new enable gpio? > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie1_default_state>; > + > + status = "okay"; > +}; > + > +&pcie1_phy { > + vdda-phy-supply = <&vreg_l3c_0p91>; > + vdda-pll-supply = <&vreg_l3e_1p2>; > + vdda-qref-supply = <&vreg_l1e_0p88>; > + > + status = "okay"; > +}; > + > &pm8550_gpios { > sdc2_card_det_n: sdc2-card-det-state { > pins = "gpio12"; Johan
On 23-02-03 10:56:31, Johan Hovold wrote: > On Fri, Feb 03, 2023 at 10:18:07AM +0200, Abel Vesa wrote: > > Enable PCIe controllers and PHYs nodes on SM8550 MTP board. > > > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > > --- > > > +&pcie_1_phy_aux_clk { > > + clock-frequency = <1000>; > > +}; > > + > > +&pcie0 { > > + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; > > + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; > > + > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie0_default_state>; > > + > > + status = "okay"; > > +}; > > + > > +&pcie0_phy { > > + vdda-phy-supply = <&vreg_l1e_0p88>; > > + vdda-pll-supply = <&vreg_l3e_1p2>; > > Super nit: add newline for consistency. > > > + status = "okay"; > > +}; > > + > > +&pcie1 { > > + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; > > + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; > > Neither controller needs the new enable gpio? Nope, none of the controllers need it. > > > + > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie1_default_state>; > > + > > + status = "okay"; > > +}; > > + > > +&pcie1_phy { > > + vdda-phy-supply = <&vreg_l3c_0p91>; > > + vdda-pll-supply = <&vreg_l3e_1p2>; > > + vdda-qref-supply = <&vreg_l1e_0p88>; > > + > > + status = "okay"; > > +}; > > + > > &pm8550_gpios { > > sdc2_card_det_n: sdc2-card-det-state { > > pins = "gpio12"; > > Johan
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index e756f83a941c..265862d0e44f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -407,6 +407,44 @@ &mdss_mdp { status = "okay"; }; +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3c_0p91>; + vdda-pll-supply = <&vreg_l3e_1p2>; + vdda-qref-supply = <&vreg_l1e_0p88>; + + status = "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12";