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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id 25-20020a05600c025900b003ed2c0a0f37sm17601988wmj.35.2023.04.26.03.49.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Apr 2023 03:49:47 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 26 Apr 2023 12:49:10 +0200 Subject: [PATCH v6 10/12] arm64: dts: mediatek: add OPP support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v6-10-8d6b1cfe7f29@baylibre.com> References: <20230203-evk-board-support-v6-0-8d6b1cfe7f29@baylibre.com> In-Reply-To: <20230203-evk-board-support-v6-0-8d6b1cfe7f29@baylibre.com> To: Catalin Marinas , Will Deacon , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat , Kevin Hilman X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3792; i=amergnat@baylibre.com; h=from:subject:message-id; bh=iQCxmnK+eQfy1aBNVxZAL4gcwl2Oh2buOTNBmT3l0E0=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkSQG/qLQtJwUDks5xtM/071v6dHlJsLh6Vt6q2cR1 FuGIjLKJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZEkBvwAKCRArRkmdfjHURS4/EA CDkZZ3jekGCJDLaK+PGqUIPjslW2V+405gqb0QmV1eD4IGEXXQV5+Andbixx64BXRH8eXQ05xz85lt l8FawZ1bhgHbtXKQ8XW5J5U3h8iBE2Oa7K2/KPBbPHz+KVxdV6uG+FphjYUu6RcwM6ZslqWIXBXLN7 wrz7/BnNjTt8vu0sDXdL1ZYQlbRrX+7PGeHokyIa7sqsC5hLzXCqvg5Gxre2RhN7w09MSbUr1CeMHR DK0Vql3GCTiHtWA5OV9ZYdGW4IZdJX+Z1sK1rByBxPWcObWw8TiosuxMdWeMebQJBsboeAwwk6g/Z3 3Gr9Tiel2eY2rRzpaphO7nB/dVPIFn+DBFJhO5h3orgncUdmOyEx2ahf1nAvly0ZVMmAWCqI2jIEdp S2RMbNgg2Z+42FiQTZeon41z7vO5aGPJvVMrccdePJDUQBNKfq8H6ZIXN8C1DDh8ZeOrd9aXB4PzEA xxxe7BRElv/bH8hi8a5u8P8eD8a89HulKYwsW/Jov77Ye5OR8RactDgbmcQ70p71HfXQjix4Auadv/ mvEbdpwCT4EsZupQGWQOzVtF/PzxVJE3rbPVAnp1po1j8ujpZ3vu1f3uGl3R6ArkyhQglD++HYbLR+ kpGrqvo6F68v3/O1Rs44x/yv9Ci4+xmsd9mlNtV51SCn7/bYhWGBd3XkEU7g== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1764235733591265624?= X-GMAIL-MSGID: =?utf-8?q?1764235733591265624?= In order to have cpufreq support, this patch adds generic Operating Performance Points support. Reviewed-by: AngeloGioacchino Del Regno Tested-by: Kevin Hilman Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 101 +++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index bb45aab2e6a9..cfe0c67ad61f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -20,6 +20,91 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <650000>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-microvolt = <668750>; + }; + + opp-987000000 { + opp-hz = /bits/ 64 <987000000>; + opp-microvolt = <687500>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <706250>; + }; + + opp-1125000000 { + opp-hz = /bits/ 64 <1125000000>; + opp-microvolt = <725000>; + }; + + opp-1216000000 { + opp-hz = /bits/ 64 <1216000000>; + opp-microvolt = <750000>; + }; + + opp-1308000000 { + opp-hz = /bits/ 64 <1308000000>; + opp-microvolt = <775000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <800000>; + }; + + opp-1466000000 { + opp-hz = /bits/ 64 <1466000000>; + opp-microvolt = <825000>; + }; + + opp-1533000000 { + opp-hz = /bits/ 64 <1533000000>; + opp-microvolt = <850000>; + }; + + opp-1633000000 { + opp-hz = /bits/ 64 <1633000000>; + opp-microvolt = <887500>; + }; + + opp-1700000000 { + opp-hz = /bits/ 64 <1700000000>; + opp-microvolt = <912500>; + }; + + opp-1767000000 { + opp-hz = /bits/ 64 <1767000000>; + opp-microvolt = <937500>; + }; + + opp-1834000000 { + opp-hz = /bits/ 64 <1834000000>; + opp-microvolt = <962500>; + }; + + opp-1917000000 { + opp-hz = /bits/ 64 <1917000000>; + opp-microvolt = <993750>; + }; + + opp-2001000000 { + opp-hz = /bits/ 64 <2001000000>; + opp-microvolt = <1025000>; + }; + }; + cpu-map { cluster0 { core0 { @@ -50,6 +135,10 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@1 { @@ -65,6 +154,10 @@ cpu1: cpu@1 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu2: cpu@2 { @@ -80,6 +173,10 @@ cpu2: cpu@2 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; cpu3: cpu@3 { @@ -95,6 +192,10 @@ cpu3: cpu@3 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2>; + clocks = <&mcucfg CLK_MCU_BUS_SEL>, + <&apmixedsys CLK_APMIXED_MAINPLL>; + clock-names = "cpu", "intermediate", "armpll"; + operating-points-v2 = <&cluster0_opp>; }; l2: l2-cache {