Message ID | 20230130213955.6046-9-ashok.raj@intel.com |
---|---|
State | New |
Headers |
Return-Path: <linux-kernel-owner@vger.kernel.org> Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp2410441wrn; Mon, 30 Jan 2023 13:44:00 -0800 (PST) X-Google-Smtp-Source: AK7set/IpJ0aXLFsuWoDIgB/Nb9M0iFfL+5cYfF/naQ/DCtp8sdKQVHFIDiHneLu6E2DDFL4OgpH X-Received: by 2002:a17:906:741:b0:87b:d3b3:94e9 with SMTP id z1-20020a170906074100b0087bd3b394e9mr14151961ejb.0.1675115040342; Mon, 30 Jan 2023 13:44:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1675115040; cv=none; d=google.com; s=arc-20160816; b=fz9jqjObsx8ot1aQGn7LDRTV3AlfUxLxMv2HT/m0qmxS73Qh5I6LVjnOTegm4T44sF DcDvHVsG6czHiFnuM+Eb9FB5T72boy7lu9hRNzZSv4upcsLsn4+BRHoA3s9TKWG71pWb Un09T8wUnQVaTd/ax2htza66Qp8fdQecDAI8hBbhf4MWRMjiqmYgRWnUwuRYRj4xowqi qAePPu/p4gB1ly1bIyhTTGCofw/WLQtQs61cQttBC6+dp4jxezeJ0u5iOtAs1VKVbkZB NzIDV0yUtP0xbfqNraLXF5PlJUQLiQ9Xil3c9QCJZPG16Xxf4SAVcgrTDsbmMBtpS82U tfOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pzDa+X67Ox698gIOboBkAKKONxsIaSH3YGbLJobMH4g=; b=fq9WsSdIBqIWNnPxbQDCni8WgbTA/WiQ1QdQqvJ9Rq5HXK+e9prNC2m4ZOw/tdfXPA ql2CqMhweZplKZ+wD91ylh+kfGYUefDQGCqJRDyvWsAvoHwsoFBRqTOnEjqrkaS7cSqD 9EzhQygs0MwFh8vb2j2NEsA69nnmnC4PlpO+S+abJSvsILe4F4C3ZwsYRGvZ0UNEK/Xh t59unYf7heIBZrdAvVAFyxc9JzbPkx78yuExMdx6Qj4ZbvgETrT6/x+vx5fYzKXbjZGl 33O4Se/sqdjmX4fFji7w0IA61jy283OXSBOhSCZ8xTp9OWBuSYaGvF1RLHjHogXsi50V uECw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ZtsGPKsH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id op27-20020a170906bcfb00b00877e1720997si14747879ejb.669.2023.01.30.13.43.36; Mon, 30 Jan 2023 13:44:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=ZtsGPKsH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229460AbjA3Vkc (ORCPT <rfc822;maxin.john@gmail.com> + 99 others); Mon, 30 Jan 2023 16:40:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231328AbjA3VkS (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Mon, 30 Jan 2023 16:40:18 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B59614E93 for <linux-kernel@vger.kernel.org>; Mon, 30 Jan 2023 13:40:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675114817; x=1706650817; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A80r7oChGS9LbqR+hFTuIEP18vZwaZTsItqNNyj9g5M=; b=ZtsGPKsHIq6wCx/m3kReHBMqDMp6+3HOE3M8RJ8Pc17FBbC/PWLjDFbW GEl50DD/VEK4FtP70OUki0VoZ6N6cCl2JW4sG19d5UjxnCxMT23IabSMU TXGkw4lQ7CZI6ske3zeKv0C+9fFj2mbF+EItV9T4SgBje9K5lcJpyWxQ1 lMUrnm5iUye5kLUm+EOnlQtNKAVs29z/hlbYyoj0u6ArSRgu8lde235FZ J9Uy0M+YznelwYX528+j4MfcdAleYTVtMI7XqUJkXSjI8koMrx6Qt0JuA gue8Eu/eL79uGUYi0fvtZRbDMeV62pZ6FFWTF5nOOf2JeR4xKfnTUZih1 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="328955565" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="328955565" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 13:40:13 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10606"; a="696571879" X-IronPort-AV: E=Sophos;i="5.97,259,1669104000"; d="scan'208";a="696571879" Received: from araj-ucode.jf.intel.com ([10.23.0.19]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2023 13:40:13 -0800 From: Ashok Raj <ashok.raj@intel.com> To: Borislav Petkov <bp@alien8.de>, Thomas Gleixner <tglx@linutronix.de> Cc: Ashok Raj <ashok.raj@intel.com>, Tony Luck <tony.luck@intel.com>, LKML <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>, Ingo Molnar <mingo@kernel.org>, Dave Hansen <dave.hansen@intel.com>, Alison Schofield <alison.schofield@intel.com>, Reinette Chatre <reinette.chatre@intel.com>, Tom Lendacky <thomas.lendacky@amd.com>, Stefan Talpalaru <stefantalpalaru@yahoo.com>, David Woodhouse <dwmw2@infradead.org>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Jonathan Corbet <corbet@lwn.net>, "Rafael J . Wysocki" <rafael@kernel.org>, Peter Zilstra <peterz@infradead.org>, Andy Lutomirski <luto@kernel.org>, Andrew Cooper <Andrew.Cooper3@citrix.com>, Boris Ostrovsky <boris.ostrovsky@oracle.com>, Martin Pohlack <mpohlack@amazon.de> Subject: [Patch v3 Part2 8/9] x86/microcode/intel: Drop wbinvd() from microcode loading Date: Mon, 30 Jan 2023 13:39:54 -0800 Message-Id: <20230130213955.6046-9-ashok.raj@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230130213955.6046-1-ashok.raj@intel.com> References: <20230130213955.6046-1-ashok.raj@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756485428866521516?= X-GMAIL-MSGID: =?utf-8?q?1756485428866521516?= |
Series |
x86/microcode: Declare microcode safe for late loading
|
|
Commit Message
Ashok Raj
Jan. 30, 2023, 9:39 p.m. UTC
Some older processors had a bad interaction when updating microcode if the caches were dirty causing machine checks. The wbinvd() was added to mitigate that before performing microcode updates. Now that Linux checks for the minimum version before performing an update, those microcode revisions can't be loaded. Early loading is also not required to use wbinvd() any longer, that was added as a safety net. Remove calls to wbinvd(). Signed-off-by: Ashok Raj <ashok.raj@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Cc: LKML <linux-kernel@vger.kernel.org> Cc: x86 <x86@kernel.org> Cc: Ingo Molnar <mingo@kernel.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Alison Schofield <alison.schofield@intel.com> Cc: Reinette Chatre <reinette.chatre@intel.com> Cc: Thomas Gleixner (Intel) <tglx@linutronix.de> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Stefan Talpalaru <stefantalpalaru@yahoo.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Rafael J. Wysocki <rafael@kernel.org> Cc: Peter Zilstra (Intel) <peterz@infradead.org> Cc: Andy Lutomirski <luto@kernel.org> Cc: Andrew Cooper <Andrew.Cooper3@citrix.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Martin Pohlack <mpohlack@amazon.de> --- arch/x86/kernel/cpu/microcode/intel.c | 12 ------------ 1 file changed, 12 deletions(-)
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 98c92b9affa2..601c586be7b6 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -415,12 +415,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) old_rev = rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -632,12 +626,6 @@ static enum ucode_state apply_microcode_intel(int cpu) goto out; } - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);