diff mbox series

[1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry

Message ID 20230126095438.354205-1-baolu.lu@linux.intel.com
State New
Headers
Series [1/1] iommu/vt-d: Set No Execute Enable bit in PASID table entry |

Commit Message

Baolu Lu Jan. 26, 2023, 9:54 a.m. UTC 
  Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
entry. It is required when XD bit of the first level page table
entry is about to be set.

Fixes: ddf09b6d43ec ("iommu/vt-d: Setup pasid entries for iova over first level")
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
---
 drivers/iommu/intel/pasid.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Tian, Kevin Jan. 28, 2023, 7:19 a.m. UTC | #1 
> From: Lu Baolu <baolu.lu@linux.intel.com>
> Sent: Thursday, January 26, 2023 5:55 PM
> 
> Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
> entry. It is required when XD bit of the first level page table
> entry is about to be set.

"is about to set" sounds like the NXE bit is set conditionally when
certain event happens. But the actual definition of NXE bit is to
allow the use of XD bit of the first level page table.

With the comment fixed:

Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Baolu Lu Jan. 28, 2023, 7:42 a.m. UTC | #2 
On 2023/1/28 15:19, Tian, Kevin wrote:
>> From: Lu Baolu<baolu.lu@linux.intel.com>
>> Sent: Thursday, January 26, 2023 5:55 PM
>>
>> Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
>> entry. It is required when XD bit of the first level page table
>> entry is about to be set.
> "is about to set" sounds like the NXE bit is set conditionally when
> certain event happens. But the actual definition of NXE bit is to
> allow the use of XD bit of the first level page table.
> 
> With the comment fixed:
> 
> Reviewed-by: Kevin Tian<kevin.tian@intel.com>

Updated. Thank you, Kevin.

Best regards,
baolu
Baolu Lu Jan. 31, 2023, 7:53 a.m. UTC | #3 
On 2023/1/26 17:54, Lu Baolu wrote:
> Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
> entry. It is required when XD bit of the first level page table
> entry is about to be set.
> 
> Fixes: ddf09b6d43ec ("iommu/vt-d: Setup pasid entries for iova over first level")
> Signed-off-by: Ashok Raj<ashok.raj@intel.com>
> Signed-off-by: Lu Baolu<baolu.lu@linux.intel.com>

Patch queued for v6.3.

https://lore.kernel.org/linux-iommu/20230131073740.378984-1-baolu.lu@linux.intel.com/

Best regards,
baolu
diff mbox series

Patch

diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
index fb3c7020028d..ec964ac7d797 100644
--- a/drivers/iommu/intel/pasid.c
+++ b/drivers/iommu/intel/pasid.c
@@ -364,6 +364,16 @@  static inline void pasid_set_page_snoop(struct pasid_entry *pe, bool value)
 	pasid_set_bits(&pe->val[1], 1 << 23, value << 23);
 }
 
+/*
+ * Setup No Execute Enable bit (Bit 133) of a scalable mode PASID
+ * entry. It is required when XD bit of the first level page table
+ * entry is about to be set.
+ */
+static inline void pasid_set_nxe(struct pasid_entry *pe)
+{
+	pasid_set_bits(&pe->val[2], 1 << 5, 1 << 5);
+}
+
 /*
  * Setup the Page Snoop (PGSNP) field (Bit 88) of a scalable mode
  * PASID entry.
@@ -557,6 +567,7 @@  int intel_pasid_setup_first_level(struct intel_iommu *iommu,
 	pasid_set_domain_id(pte, did);
 	pasid_set_address_width(pte, iommu->agaw);
 	pasid_set_page_snoop(pte, !!ecap_smpwc(iommu->ecap));
+	pasid_set_nxe(pte);
 
 	/* Setup Present and PASID Granular Transfer Type: */
 	pasid_set_translation_type(pte, PASID_ENTRY_PGTT_FL_ONLY);