From patchwork Thu Jan 26 08:53:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 48530 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:eb09:0:0:0:0:0 with SMTP id s9csp171178wrn; Thu, 26 Jan 2023 00:55:07 -0800 (PST) X-Google-Smtp-Source: AMrXdXvp8kZSDjGdzWigJ9vZZ4ubNj3ZL5xX8fKxC8erQFbYTS5J9+2J8SCHCAK1fWLvlVGWxURD X-Received: by 2002:a05:6402:520a:b0:49e:a080:d55f with SMTP id s10-20020a056402520a00b0049ea080d55fmr34845234edd.18.1674723306795; Thu, 26 Jan 2023 00:55:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1674723306; cv=none; d=google.com; s=arc-20160816; b=ZGunDn6ra1ICwMC9OARTUaJoo5iWzNXpqv7Mqn6OohF9YydXwNWFE6X3EeQo4KBi7g Ph5fBfcyUQpOVg6S9C0lcIWD/bMoPOoucCgsLQKQ0APmeFiSOg3fL9gmrb3u8q26BSaX ydEKLmnAk7y0gqSENep3/w79ALcFHrQbLO2ohL82ixbXdOnPWAkroLGEbqJ/OycxyLYr Sj+pP7Ml41yhJREU6YyWEAYLwY3iz4q1s4DzcE3tz6CTRYTymt7H6ImztoXn8musFM1y oY9R9KbpuMfKOuUPosIZF/nORgdeh3ni/YBeZHW9mU0HqTHYWFMQkF5to/2SnmSMoRMl LC5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=98GKHzs+Q+U5QKL1M6+pcEb92KXffmqsyafWr6vk4nA=; b=I7kpNrgNvQ26/aTa2bneXApQ9GKpDtPMBAVXZ3C0HZRjaB4153zdwFFae7qvkHKTeA gInNN7wOGlN1ihSjJVKeClphAmVNixEg/e39MaXme3MkVlBNzxSMmj8Za4IDO14prUnt AbFi9mFrP/zHOOSaUkxIXtofbuxHL3kpf9ZdUNDkuJEsVk7/Pzr/96LKdroSbEdb0hLy bwLrqYn1j/mGbGd4Ul1Jm4C7tPVNaqM9hztTwClUk2Sl5hs17mKVTF8kH1+wBJDqww/o kjddFhZo3VCDlveeHVtSESHz7tu4EvzJKtnOElE/W8WSYA4J1i4wRoGnkHoA6+XV+Uj2 SSZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=nJ7Dp18r; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id d11-20020a50fb0b000000b0048aa3eebb6dsi1157733edq.611.2023.01.26.00.54.42; Thu, 26 Jan 2023 00:55:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=nJ7Dp18r; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236604AbjAZIx6 (ORCPT + 99 others); Thu, 26 Jan 2023 03:53:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236552AbjAZIxs (ORCPT ); Thu, 26 Jan 2023 03:53:48 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAED139CE2; Thu, 26 Jan 2023 00:53:43 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 0C48F6602E8A; Thu, 26 Jan 2023 08:53:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1674723213; bh=pKMGoeKu4m5DJFVWyByEtDagZ1PUSFRsRa3TlZzOsdw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nJ7Dp18rXaD2PV9bjGm7alMnY0xRZiSN3N9p5TcIvxR5VTV6i/O0VR+aW99bNveuH rTOTug+CjPQAiqqtDJnpikOkJhiCASTHZQhE8ag9xqZG7HiicGlxXwsmC3lPov0GGl Xtg9SRAFsWqIEL6k489ZSK0lyk4a59UNiUUK2eeVz4THuLbt59UMsGeHFkQxJKJvKY EDsHuPUxrxA3OKTERdnc9iVpJXPN15DG8KD2sh9347lNgShJeiAez4AxXnZZ7UHC39 3NQPW93pbcQnloqQ7M1jgxqy7TaNABbCDWN93ke7i707wJK89rUp0DzU7YEgiuu/jg E4NW9pyHuFVGg== From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: mturquette@baylibre.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, edward-jw.yang@mediatek.com, johnson.wang@mediatek.com, wenst@chromium.org, miles.chen@mediatek.com, chun-jie.chen@mediatek.com, rex-bc.chen@mediatek.com, jose.exposito89@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com Subject: [PATCH v2 6/6] clk: mediatek: mt8195: Add support for frequency hopping through FHCTL Date: Thu, 26 Jan 2023 09:53:21 +0100 Message-Id: <20230126085321.87267-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> References: <20230126085321.87267-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756074666060985185?= X-GMAIL-MSGID: =?utf-8?q?1756074666060985185?= Add FHCTL parameters and register PLLs through FHCTL to add support for frequency hopping and SSC. FHCTL will be enabled only on PLLs specified in devicetree. This commit brings functional changes only upon addition of devicetree configuration. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 69 +++++++++++++++++++- 1 file changed, 66 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 1bc917f2667e..c0db31ce0741 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -3,9 +3,11 @@ // Copyright (c) 2021 MediaTek Inc. // Author: Chun-Jie Chen +#include "clk-fhctl.h" #include "clk-gate.h" #include "clk-mtk.h" #include "clk-pll.h" +#include "clk-pllfh.h" #include #include @@ -105,6 +107,61 @@ static const struct mtk_pll_data plls[] = { 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9), }; +enum fh_pll_id { + FH_ARMPLL_LL, + FH_ARMPLL_BL, + FH_MEMPLL, + FH_ADSPPLL, + FH_NNAPLL, + FH_CCIPLL, + FH_MFGPLL, + FH_TVDPLL2, + FH_MPLL, + FH_MMPLL, + FH_MAINPLL, + FH_MSDCPLL, + FH_IMGPLL, + FH_VDECPLL, + FH_TVDPLL1, + FH_NR_FH, +}; + +#define FH(_pllid, _fhid, _offset) { \ + .data = { \ + .pll_id = _pllid, \ + .fh_id = _fhid, \ + .fh_ver = FHCTL_PLLFH_V2, \ + .fhx_offset = _offset, \ + .dds_mask = GENMASK(21, 0), \ + .slope0_value = 0x6003c97, \ + .slope1_value = 0x6003c97, \ + .sfstrx_en = BIT(2), \ + .frddsx_en = BIT(1), \ + .fhctlx_en = BIT(0), \ + .tgl_org = BIT(31), \ + .dvfs_tri = BIT(31), \ + .pcwchg = BIT(31), \ + .dt_val = 0x0, \ + .df_val = 0x9, \ + .updnlmt_shft = 16, \ + .msk_frddsx_dys = GENMASK(23, 20), \ + .msk_frddsx_dts = GENMASK(19, 16), \ + }, \ + } + +static struct mtk_pllfh_data pllfhs[] = { + FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78), + FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c), + FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8), + FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0), + FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104), + FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118), + FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c), + FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140), + FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154), +}; + static const struct of_device_id of_match_clk_mt8195_apmixed[] = { { .compatible = "mediatek,mt8195-apmixedsys", }, {} @@ -114,13 +171,17 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; + const u8 *fhctl_node = "mediatek,mt8195-fhctl"; int r; clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; - r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs)); + + r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls), + pllfhs, ARRAY_SIZE(pllfhs), clk_data); if (r) goto free_apmixed_data; @@ -140,7 +201,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev) unregister_gates: mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); unregister_plls: - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); free_apmixed_data: mtk_free_clk_data(clk_data); return r; @@ -153,7 +215,8 @@ static int clk_mt8195_apmixed_remove(struct platform_device *pdev) of_clk_del_provider(node); mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); - mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs, + ARRAY_SIZE(pllfhs), clk_data); mtk_free_clk_data(clk_data); return 0;