Message ID | 20230126045738.47903-11-samuel@sholland.org |
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State | New |
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Wed, 25 Jan 2023 23:57:49 -0500 (EST) From: Samuel Holland <samuel@sholland.org> To: Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, linux-sunxi@lists.linux.dev Cc: linux-riscv@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>, Palmer Dabbelt <palmer@dabbelt.com>, Conor Dooley <conor@kernel.org>, Jisheng Zhang <jszhang@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>, Rob Herring <robh+dt@kernel.org>, linux-arm-kernel@lists.infradead.org, Samuel Holland <samuel@sholland.org>, Conor Dooley <conor.dooley@microchip.com>, Palmer Dabbelt <palmer@rivosinc.com>, Guo Ren <guoren@kernel.org> Subject: [PATCH v5 10/11] riscv: Add the Allwinner SoC family Kconfig option Date: Wed, 25 Jan 2023 22:57:37 -0600 Message-Id: <20230126045738.47903-11-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20230126045738.47903-1-samuel@sholland.org> References: <20230126045738.47903-1-samuel@sholland.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1756060141128095388?= X-GMAIL-MSGID: =?utf-8?q?1756060141128095388?= |
Series |
riscv: Allwinner D1/D1s platform support
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Commit Message
Samuel Holland
Jan. 26, 2023, 4:57 a.m. UTC
Allwinner manufactures the sunxi family of application processors. This includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8 SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs. The first SoC in the sun20i series is D1, containing a single T-HEAD C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM. Most peripherals are shared across the entire chip family. In fact, the ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible with the D1s. This means many existing device drivers can be reused. To facilitate this reuse, name the symbol ARCH_SUNXI, since that is what the existing drivers have as their dependency. Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Samuel Holland <samuel@sholland.org> --- (no changes since v4) Changes in v4: - Drop the now-redundant 'select SIFIVE_PLIC' - Rebase on v6.2-rc1 + soc2arch-immutable Changes in v3: - ARCH_SUNXI depends on MMU && !XIP_KERNEL Changes in v2: - Sort Kconfig as if we had done s/SOC_/ARCH_/ for future-proofing arch/riscv/Kconfig.socs | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 659140309157..1cf69f958f10 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -32,6 +32,15 @@ config SOC_STARFIVE help This enables support for StarFive SoC platform hardware. +config ARCH_SUNXI + bool "Allwinner sun20i SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_THEAD + select SUN4I_TIMER + help + This enables support for Allwinner sun20i platform hardware, + including boards based on the D1 and D1s SoCs. + config ARCH_VIRT def_bool SOC_VIRT